Electronics Forum | Mon May 14 17:12:20 EDT 2001 | davef
Continuing along the path that Brian took ... IPC-7525 gives design guideline for stepped stencils. It goes something like: * Stepped area SB GT 25 thou from pads located on the greatest thickness of the stencil * Pads in stepped area SB GT 35 tho
Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F
=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so
