Electronics Forum | Fri Jun 22 11:54:47 EDT 2001 | jdtpfacreate
OEM Boy, This is an excellent question. Since I am on the "I-want-to-sell-you-equipment-side" I do not have the hands-on experience that you do but, I do have a many engineers back at our factory who have dedicated their lives to these issues.
Electronics Forum | Thu Jun 14 23:21:30 EDT 2001 | oem boy
I am working on 0201 development for my company in the UK, and I am planning a rather extensive DOE for my reflow oven profile. I am planning on studying various ramp rates, soak times, times above liquidus, peak temps, etc... My biggest concern
Electronics Forum | Fri Feb 22 13:24:24 EST 2008 | mulder0990
How did I know senior was going to get in here too. Nice to see you again. I figured as much with the height difference, but I do not have the equipment here to test my thoughts. We somehow have our machine dialed in to run the 0201 parts with W
Electronics Forum | Fri Sep 10 15:15:09 EDT 2021 | majdi4
Hello to all , Could you help with this defect .. Tombstoning 0201 , always at the same place in board , only this component near to the coax connector..with a defect rate of 2 % ..All the process is perfect . i cheked : stencil design , SPI resul
Electronics Forum | Mon Sep 27 10:53:24 EDT 2021 | majdi4
Thank you all for your quick reply ! the problem is solved without making any intervention on line .. 0% defect rate for the moment .. for all of you who said "try rotating the board 180 °", we can't do that because the panel contains 2 boards head t
Electronics Forum | Sat Jan 15 13:13:33 EST 2000 | Mark Wiegold
Steve, Basically in answer to your question, there is no real set number for defects. Defect rates will vary between products and companies. If my company was running the same product as yourself then there is no reason to suggest that the defect ra
Electronics Forum | Fri Jan 14 16:48:40 EST 2000 | Steve Thomas
O.K., folks, I know this is a loaded question, but I've been asked to find the answer, sooooo: What is an acceptable defect rate in ppm for a surface mount process, assuming that each component has the potential for one defect. This would include de
Electronics Forum | Tue Jan 18 20:31:10 EST 2000 | WDavidson
It makes a difference what the normalizer is. We calculate solder ppm and placement ppm separately for each assembly. Solder ppm = #solder defects*1E6/(Qty boards*#solder joints per board). For us this number is easily less than 50 and sometimes
Electronics Forum | Sat Jan 15 16:59:47 EST 2000 | Steve Thomas
Thanks, Mark. Actually we already have an established mark. We use 500ppm (99.95%) as our acceptable level. Problem is, someone (another manufacturer) told someone else (our pres.) that THEY build to 50ppm. Soooooo, someone else told my boss that
Electronics Forum | Mon Jan 17 12:16:02 EST 2000 | Brian W.
My old company (CM) ran SMT to 50ppm including some very complex boards. We established the normalizer number by: #components + #solder joints. As was stated earlier, the ppm for any given product is the result of many factors. You may get differen
