Electronics Forum | Thu Sep 24 18:57:03 EDT 2009 | davef
From "siliconfareast.com": Basic Die Cracking FA Flow 1) Failure Information/Device and Lot History Review. Understand the customer's description of the failure, i.e., the failure mode, where it was encountered, what conditions the sample was subject
Electronics Forum | Thu Sep 24 09:25:24 EDT 2009 | davef
What do you mean by "substrate?" Is it: * Semiconductor die * BT circuit board interposer Is the BGA package: * Encapsulated * Mounted on a circuit board
Electronics Forum | Mon Sep 19 07:34:14 EDT 2011 | henrytcx89
I would like to ask a few things about die crack. 1. I would like to know what could possibly be the root cause of die crack in die preparation? (Saw machine? Pick and Place machine?) 2. May I know how could I solve the problem? Thank you very muc
Electronics Forum | Mon Sep 19 09:25:29 EDT 2011 | tech1
There are a few questions I have before we can answer this: 1. How are the die presented to the pick and place machine? (Tape, waffle Pak, tray) 2. What are the dimensions of the die (LxWxH)? 3. Are they bumped die? 4. What is the material of the
Electronics Forum | Mon Sep 19 19:22:11 EDT 2011 | henrytcx89
Thanks for taking ur time to answer this. =) The pick and place machine is just pick from wafer(on tape) and place into waffle pack. I read from some of the sources saying that the ejecting needle and the vacuum pick up bits could cause the die to c
Electronics Forum | Sat Sep 24 16:06:13 EDT 2011 | tech1
Okay so you are picking from a Wafer Frame and it is a UV cured tape. Who's die sorting machine are you using? You mention the ejector needles, but have you checked them? What size are the die and how thick are they? Have you checked the UV cure, i
Electronics Forum | Mon Jun 18 18:17:10 EDT 2001 | davef
What to you consider to be the minimum resolution [micron] for: General, BGA, die attach uBGA, flipchip, wire bonds Wire cracks, delamination Microcircuit failure What is the relationship between resolution [micron] and the kV of the tube?
Electronics Forum | Tue Oct 26 11:01:54 EDT 2004 | Simon UK
DO you have an xray onsite? One suggestion is to check what you can with that machine, i know it wont be able to magnify to 200nm or something, but it will show any ESD damage to the wire bonds or any major cracks of the silicon die. P.s. Most devi
Electronics Forum | Mon Oct 06 11:13:32 EDT 2003 | marmotzj
Dear All, I'm encountering a problem on mounting Intel E7501 and P64H2 FC-BGA chips. After the SMT process, these two BGAs were defected. Both had power-to-ground short circuits on the die package itself, and also the die resin had cracking tracks
Electronics Forum | Thu Feb 11 08:14:41 EST 2010 | scottp
It's OK to have the daisychain done in the interposer rather than the die (and a lot cheaper) but in thermal cycling the parts MUST have representative die. That's where a large part of the CTE mismatch comes from to cause fatigue damage. Thermal c
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