Electronics Forum | Mon Feb 12 10:02:18 EST 2007 | rgduval
A little late to the party here, sorry... Has the joint been verified as a cold solder joint? That is, visually confirmed that it looks like cold solder, and, perhaps, xrayed to confirm the solder status? X-raying may sound a bit extreme, but you'
Electronics Forum | Mon Apr 17 19:30:27 EDT 2000 | Boca
All of the above is good stuff. To add, I have seen this several times if the assembly is wavesoldered. Heat from the wave can partially reflow the top side SM solder joints and weaken them. To test, check joint strength before wave and then after
Electronics Forum | Tue Apr 11 16:42:56 EDT 2000 | Chad Notebaert
I�m thinking �Poor intermatallic� It could be a few things. Lets start at the beginning. -Is your paste a 63/37 mixture? -Have you monitored you screen printing, Verify Solder deposition, Are you getting enough paste? -You say the solder looks like i
Electronics Forum | Mon Mar 22 09:37:28 EST 2004 | ellis
After 2nd time reflow of double reflow, wrinkles solder joints found on SOIC and SOT components.(only happen on the components at the underside of pcb during reflow, top side components dont have this problem) is this due to the reflow process proble
Electronics Forum | Mon May 27 04:46:11 EDT 2019 | SMTA-Rogers
Dear CW, Yes, we also tested many different brands and models of solder paste, under the same stencil design and reflow profile the condition of the voids will have great difference.
Electronics Forum | Tue May 07 10:13:06 EDT 2019 | cyber_wolf
I have personally never seen a reflow profile change reduce voids. We have invited "experts" in to demonstrate this claim. They were unable to.
Electronics Forum | Mon May 27 04:36:08 EDT 2019 | SMTA-Rogers
Dear Sr.Tech, We tried to adjust the soak time and TAL time of reflow profile, but it doesn’t seem to help much.
Electronics Forum | Mon May 27 04:40:21 EDT 2019 | SMTA-Rogers
Dear Steve, We already to do some DOE of reflow profile, but the optimized parameters are not help for the reduction of voids.
Electronics Forum | Mon Mar 22 10:24:03 EST 2004 | davef
Wrinkled like orange peel?
Electronics Forum | Mon May 06 06:22:39 EDT 2019 | SMTA-Rogers
Hello! Do you have a better stencil design to reduce the large area of solder joint voids? Or is there a suggested way to set the reflow profile? Or are there other process improvements to make the solder joint at the LED pad less than 10% per void?
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