Electronics Forum: through package vias (Page 3 of 66)

Plated through via's in pads.

Electronics Forum | Thu Feb 06 14:47:50 EST 2003 | MA/NY DDave

Hi "some customers/designers want to have via holes to be present in the PCB pad, due to some belief that it helps in heat dissipation. " As I think about this I don't know exactly why they would be concerned. I can imagine in some exotic products

Plated through via's in pads.

Electronics Forum | Wed Feb 05 11:21:24 EST 2003 | pjc

First off, get them designed out. I had this problem once and filled them with SMD adhesive and cured prior to printing. We were careful to be sure the solder lands were clean of any adhesive prior to curing. It worked out very well and we did this p

Plated through via's in pads.

Electronics Forum | Mon Feb 10 05:32:44 EST 2003 | matherat

BPan, I would like to discuss a possible solution to this that involves some of the suggestions found here but, with a twist that our process offers. This would be better discussed one on one somewhere other than this forum so if you still need sugg

Plated through via's in pads.

Electronics Forum | Mon Feb 10 21:30:48 EST 2003 | MA/NY DDave

Hi You are probably right. The only thing I will tell you is that one time as thee DFM engineer working between many electronic designers, component manufacturers and CEMs (contract electronic manufacturers) the component manufacturer would not bud

6 layer board and routing bga package

Electronics Forum | Fri Feb 19 05:14:04 EST 2016 | truewanderer

Hi, i have a confusion to read the dimension of BGA package from the datasheet. I have attached the datasheet below. Is this diameter of the ball 0.30mm or 0.15mm. I'm confused about the values given in the box. Whats meant by M, S, A and B. Please g

automatic placement of pin through hole component

Electronics Forum | Wed Feb 09 08:54:42 EST 2000 | pascal MATHIEU

Hello friends , in order to try to reduce our labour cost , we are thinking to replace manual placementof PTH COMPONENTS by automatic unit which 'll be able to place relays ,and connectors . is there anybody on this forum to advise us on this topi

Why 50 mils in 0805 package instead of 40 mils.

Electronics Forum | Mon Oct 06 08:51:26 EDT 2003 | davef

The EIA does not provide that information. EIA standards focus on component dimensions. Alternately consider: ...cut... SM-782A - Surface Mount Design & Land Pattern Standard, Inc. Am. 1 & 2 ANSI Approved Get up-to-date land pattern recommendat

solder question on crystal in DFN style package

Electronics Forum | Mon Apr 05 16:12:16 EDT 2010 | dyoungquist

We are installing via reflow soldering a crystal that has 2 pads, 1 each end. They are flat pads on the bottom of the part with a small area of the pad looping around and up the side of the crystal on the end. Inspection of the cyrstal under a 40X

Re: More informations on water clean for CSP/BGA package

Electronics Forum | Wed Oct 06 11:40:41 EDT 1999 | Debbie Alavezos

| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n

Re: More informations on water clean for CSP/BGA package

Electronics Forum | Wed Oct 06 03:58:25 EDT 1999 | Brian

| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n


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