Electronics Forum | Wed Sep 15 22:43:24 EDT 2004 | davef
Just to help convince those on the fence that we don't know dip: 2221A, 4.5.1 tells you the vias have to be tented on both sides.
Electronics Forum | Wed Mar 23 22:28:10 EST 2005 | KEN
I ran into this yesterday. Seems some designer decided to not solder resist the via's on the solder side. Then the assembly went over the wave solder in a universal fixture. Not an ideal situation.
Electronics Forum | Fri Dec 01 15:22:46 EST 2017 | kojotssss
Recommended land and solder pattern says: VIA wall plating, via holes should be tented with solder mask on the backside and filled with solder. Solutions at this moment ? Thanks for all :)
Electronics Forum | Thu Oct 28 15:53:27 EDT 2010 | dwonch
Ok, just to put closure on things I figured I should post the conclusion of this whole ordeal. We've acquired a new BGA rework station that allows us to get away without tenting our vias under the BGAs. This allowed us to change our PCB spec to rem
Electronics Forum | Sun Feb 05 09:49:11 EST 2006 | Cmiller
We have been using ENIG for 8 years as our primary board finish. We have not seen any issues with tenting the vias. We have used a number of suppliers. The ENIG from China does not seem to solder quite as well in general but only had black pad from o
Electronics Forum | Mon Apr 22 15:05:47 EDT 2002 | tim_easterling
Depending on the volume of boards you are manufacturing, the most cost effective solution would be to epoxy plug the vias prior to LPI soldermask application. The technique is common practice and most suppliers can provide it will little or no cost a
Electronics Forum | Fri Jan 21 16:50:33 EST 2005 | Board House
I work for a board house and our proceedure for this process is the following, We cover the via pads leaving the hole open and then apply the surface finish and then go back and Cover the Via with a second operation. By doing this you do not entrap
Electronics Forum | Fri Feb 22 14:22:07 EST 2008 | stevek
Are you using nocleans, especially when you get to SMT? Years ago, I had OA wave flux get into vias that were plugged from the top under parts. It is really difficult to clean small, high aspect ratio vias. Cross sections showed that the copper in
Electronics Forum | Sat May 18 15:19:55 EDT 2013 | isd_jwendell
OK, I've now read all of the documents you referenced. The problem still remains regarding the thermal vias and how to minimize scavenging. All the docs acknowledge top and bottom tenting, and it's problems. TI says don't do it. Plugging is usually n
Electronics Forum | Mon Jul 26 18:05:18 EDT 1999 | ScottM
| Presently protos of micro-bgas (80i/o) pitch .030/.031 | 12BGA per assembly | | The board is a (.062, 4 layers) FR-4 using Dry film | Pads .014inch | Vias within footprint .020inch | Vias to be filled by bottom side(solder side) only .030in dia. F
