Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2023-01-17 17:19:44.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2011-12-29 17:33:21.0
2011 IPC APEX EXPO Conference Article: Surface mount area arrays (SMAA) have been in existence for decades and are increasingly becoming more important as printed circuit board (PCB) assemblies become further complex with package miniaturization and densi
Technical Library | 2012-12-27 14:35:29.0
Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2014-05-01 15:14:12.0
Bilayer graphene has been a subject of intense study in recent years. The interlayer registry between the layers can have dramatic effects on the electronic properties: for example, in the presence of a perpendicular electric field, a band gap appears in the electronic spectrum of so-called Bernal-stacked graphene. This band gap is intimately tied to a structural spontaneous symmetry breaking in bilayer graphene, where one of the graphene layers shifts by an atomic spacing with respect to the other. This shift can happen in multiple directions, resulting in multiple stacking domains with soliton-like structural boundaries between them
Technical Library | 2015-01-05 17:38:26.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC-9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2016-11-03 17:53:56.0
We present a novel method for fabricating a high-density carbon nanotube microelectrode array (MEA) chip. Vertically aligned carbon nanotubes (VACNTs) were synthesized by microwave plasma-enhanced chemical vapor deposition and thermal chemical vapor deposition. The device was characterized using electrochemical experiments such as cyclic voltammetry, impedance spectroscopy and potential transient measurements. Through-silicon vias (TSVs) were fabricated and partially filled with polycrystalline silicon to allow electrical connection from the high-density electrodes to a stimulator microchip.In response to the demand for higher resolution implants, we have developed a unique process to obtain a high-density electrode array by making the microelectrodes smaller in size and designing new ways of routing the electrodes to current sources.
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