Technical Library | 2023-01-17 17:12:33.0
Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.
Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2007-12-13 17:03:02.0
Printer-hosted processes for solder ball placement are now widely used for package technologies ranging from BGAs using ball diameters above 750μm to the latest WL-CSPs demanding 250μm diameter. This broadening spectrum of applications brings more choices in terms of stencil design rules and production methodologies.
Technical Library | 2007-09-27 16:18:15.0
Considerable interest exists in the process known as the pinin- paste, or the Alternative Assembly and Reflow Technology (AART) process. The AART process allows for the simultaneous reflow of both odd-form and through hole devices as well as surface mount components. This process has several advantages over the typical mixed technology process sequence that includes wave soldering and/or hand soldering, often in addition to reflow soldering.
Technical Library | 2007-06-13 13:44:10.0
Very high performance computer applications have created a demand for large organic substrates capable of interconnecting one or a few ASIC semiconductor devices with packaged memory devices. The electrical advantages offered by the use of a thin PTFE composite substrate were coupled with intrinsic mechanical advantages to create very high performance applications. The application development required interactions of design, fabrication, and new manufacturing technology to obtain rapid prototype production and allow a successful ensuing manufacturing ramp.
Technical Library | 2012-01-26 20:28:34.0
In electronics design, Computer Aided Design (CAD) tools manage part data in a logical schematic view (a part symbol) and a physical PCB view (a part footprint). Yet, a part has a third view, which CAD tools ignore – its supply data (Manufacturer part num
Technical Library | 2014-07-17 17:01:10.0
Embedded computing systems used in many military and avionics applications are trending toward higher heat fluxes, and as a result performance is being hindered by thermal limitations. This is intensified by the high ambient conditions experience by today’s modern warfighter. In many applications liquid cooling is replacing air flow through chassis for both thermal and environmental benefits(...) This paper outlines a series of passive thermal improvements which are easily integrated into legacy, or existing, systems and can provide a 3-4x increase in dissipated power.
Technical Library | 2017-03-02 18:13:05.0
The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS) transistors has become a major concern as the power consumption of electronic integrated circuits (ICs) steadily increases with technology scaling. Nano-Electro-Mechanical (NEM) relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays) have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.
Technical Library | 2015-04-23 18:48:18.0
Smart phones are complex, costly devices and therefore need to be reworked correctly the first time. In order to meet the ever-growing demand for performance, the complexity of mobile devices has increased immensely, with more than a 70% greater number of packages now found inside of them than just a few years ago. For instance, 1080P HD camera and video capabilities are now available on most high end smart phones or tablet computers, making their production more elaborate and expensive. The printed circuit boards for these devices are no longer considered disposable goods, and their bill of materials start from $150.00, with higher end smart phones going up to $238.00, and tablets well over $300.00.
Technical Library | 2021-11-22 20:32:10.0
The aim of this work is to define a procedure to develop diagnostic systems for Printed Circuit Boards, based on Automated Optical Inspection with low cost and easy adaptability to different features. A complete system to detect mounting defects in the circuits is presented in this paper. A low cost image acquisition system with high accuracy has been designed to fit this application. Afterward, the resulting images are processed using the Wavelet Transform and Neural Networks, for low computational cost and acceptable precision. The wavelet space represents a compact support for efficient feature extraction with the localization property. The proposed solution is demonstrated on several defects in different kind of circuits.
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