Technical Library | 2008-05-28 18:41:53.0
This paper describes correlation between a true 2D area measurement (e.g. printer) and a height map generated area from a SPI system. In addition, this paper will explore the correlation between area/volume measurements and bridge detection between 2D/3D techniques. The ultimate goal is to arm the process engineers with information that can be used to make decision that will impact defects, cost, throughput and Return On Investment.
Technical Library | 2018-02-01 00:31:48.0
This paper briefly summarizes the technologies underpinning the evolution in electrical system diagnosis and repair, which include schematic layout automation using prototypes and rule-based styling, instant language translation, 2D/3D view links with schematics, interactive diagnostic procedures, and dynamically-generated signal-tracing diagrams. These technologies empower after-sales service teams with state-of-the-art capabilities, which not only reduce costs but also improve brand quality in the eyes of its customers.
Technical Library | 2010-09-16 18:45:06.0
With PCB complexity and density increasing and also wider use of 3D devices, tougher requirements are now imposed on device inspection both during original manufacture and at their subsequent processing onto printed circuit boards. More complicated and de
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2023-11-20 17:36:58.0
With PCB complexity and density increasing and also wider use of 3D devices, tougher requirements are now imposed on device inspection both during original manufacture and at their subsequent processing onto printed circuit boards. More complicated and dense packages have more opportunities to exhibit defects both internal to the package as well as to the PCB. As components increase in complexity their cost increases, making counterfeiting them a potentially lucrative business for unscrupulous individuals and organizations.
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