Technical Library | 2015-07-14 13:19:10.0
Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names, such as QFN (quad flat no lead), DFN (dual flat no lead), LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance. However, bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint, especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns.
Technical Library | 2013-06-13 15:31:24.0
Electromigration (EM) is a mass transportation mechanism driven by electron wind force, thermal gradient, chemical potential and stress gradient. According to Moore’s law, number of transistors on integrated circuits (ICs) doubles approximately every 2 years. Moore’s law holds true since its introduction in 1970s. This insatiable demand for smaller ICs size, larger integration and higher Input/Output (IO) count of microelectronics has made ball grid array (BGA) the most promising connection type in electronic packaging industry. This trend, however, renders EM reliability of solders joints a major bottleneck to hinder further development of electronics industry...
Electronic Packaging Laboratory, State University of New York
Technical Library | 2014-06-05 16:44:07.0
Stencil printing capability is becoming more important as the range of component sizes assembled on a single board increases. Coupled with increased component density, solder paste sticking to the aperture sidewalls and bottom of the stencil can cause insufficient solder paste deposits and solder bridging. Yield improvement requires increased focus on stencil technology, printer capability, solder paste functionality and understencil cleaning.(...) The purpose of this research is to study the wipe sequence, wipe frequency and wipe solvent(s) and how these factors interact to provide solder paste printing yield improvement.
Technical Library | 2021-08-25 16:34:37.0
As the traditional eutectic SnPb solder alloy has been outlawed, the electronic industry has almost completely transitioned to the lead-free solder alloys. The conventional SAC305 solder alloy used in lead-free electronic assembly has a high melting and processing temperature with a typical peak reflow temperature of 245ºC which is almost 30ºC higher than traditional eutectic SnPb reflow profile. Some of the drawbacks of this high melting and processing temperatures are yield loss due to component warpage which has an impact on solder joint formation like bridging, open defects, head on pillow.
Technical Library | 2017-12-11 22:31:06.0
Typical printed circuit board assemblies (PCBAs) processed by reflow, wave, or selective wave soldering were analysed for typical levels of process related residues, resulting from a specific or combination of soldering process. Typical solder flux residue distribution pattern, composition, and concentration are profiled and reported. Presence of localized flux residues were visualized using a commercial Residue RAT gel test and chemical structure was identified by FT-IR, while the concentration was measured using ion chromatography, and the electrical properties of the extracts were determined by measuring the leak current using a twin platinum electrode setup. Localized extraction of residue was carried out using a commercial C3 extraction system. Results clearly show that the amount and distribution of flux residues are a function of the soldering process, and the level can be reduced by an appropriate cleaning. Selective soldering process generates significantly higher levels of residues compared to the wave and reflow process. For conformal coated PCBAs, the contamination levels generated from the tested wave and selective soldering process are found to be enough to generate blisters under exposure to high humidity levels.
Technical Library | 2008-03-31 21:35:36.0
While the situation varies from country to country, nearly one year after the EU RoHS Directive came into force implementation of lead-free solder is progressing steadily. For lead-free soldering to be considered successful it is not sufficient just to have dealt with the challenges of mass production. It is also necessary to establish that the soldered joints produced are at least as reliable as those made with Sn-37Pb alloy. In this context "reliability" means the length of time in service that the initial functionality of the joint can be maintained. In this paper we will discuss some of the issues involved in solder joint reliability through a comparison of the properties of two alloys that are widely used for lead-free wave soldering, SAC305 (Sn-3.0Ag-0.5Cu) and the Sn, Cu, Ni, Ge alloy SN100C.
Technical Library | 2022-03-16 19:48:18.0
Dendrites, Electrochemical Migration (ECM) and parasitic leakage, are usually caused by process related contamination. For example, excess flux, poor handling, extraneous solder, fibers, to name a few. One does not normally relate these fails with environmental causes. However, creep corrosion is a mechanism by which electronic products fail in application, primarily related to sulfur pollution present in the air.1 The sulfur reacts with exposed silver, and to a lesser extent, exposed copper. This paper will explore various aspects of the creep corrosion chemical reaction
Technical Library | 2015-04-29 03:48:39.0
SPI equipment is routinely used in Printed Circuit Board (PCB) manufacturing to monitor and control one of the most crucial steps affecting the finished quality of circuit board. Solder paste deposition is the key process in board assembly operations using SMT techniques. Our LSM™ system was the industry's first popular method of manually inspecting solder paste; our SE systems revolutionized SMT production by offering an automated method for performing in-process 3D inspection on the assembly line. SPI systems measure the height and volume of the solder pads before the components are applied and the solder melted, and when used properly, can reduce the incidence of solder-related defects to statistically insignificant amounts. Critical to the SPI measurement is the accuracy of the height measurement because that has a direct correlation with solder volume and defects.
Technical Library | 2007-04-05 13:48:50.0
Recently a large global player approached us with a problem. They needed an initial assembly solution for brand new components. Their boards and CSP specimens could not safely be soldered due to wetting problems at the solder joints.
Technical Library | 2022-10-31 18:35:40.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
.png)