Industry News | 2017-08-30 16:58:11.0
Akrometrix will be a panelist in the upcoming SMTAI Spotlight 5 panel discussion, scheduled to take place Wednesday, Sept. 10, 2017 from 2-3 p.m. The discussion, entitled “Warpage Induced Defects and Component Warpage Limits,” will be streamed on Facebook Live.
Industry News | 2024-09-30 20:02:53.0
PEMTRON is pleased to announce its participation in NEPCON Nagoya 2024, where it will showcase its cutting-edge equipment designed for precision inspection in semiconductor and electronics manufacturing. From October 23-25, visitors to PEMTRON's booth will experience demonstrations of the JUPITER 3D X-ray Inspection System, POSEIDON Wafer Warpage Measurement and FC-BGA Bump Inspection System, APOLLON Package Inspection System, and the 8800WIR Wafer Inspection System.
Industry News | 2019-11-05 22:08:21.0
Via in pad is the design practice of placing a via in the copper landing pad of a component. Compared to standard PCB via routing, via in pad allows a design to use smaller component pitch sizes and further reduce the PCBs overall size. With component manufactures pushing smaller parts every year and the demand from consumers for smaller devices, the usage of via in pad practices by hardware engineers have become more commonplace. In this article, we will discuss the differences between via in pad and traditional vias, when should you use via in pad, and how to design for it.
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