Technical Library | 2021-01-03 19:24:52.0
Reflow soldering is the primary method for interconnecting surface mount technology (SMT) applications. Successful implementation of this process depends on whether a low defect rate can be achieved. In general, defects often can be attributed to causes rooted in all three aspects, including materials, processes, and designs. Troubleshooting of reflow soldering requires identification and elimination of root causes. Where correcting these causes may be beyond the reach of manufacturers, further optimizing the other relevant factors becomes the next best option in order to minimize the defect rate.
Technical Library | 2014-10-23 18:10:10.0
The functional reliability of electronic circuits determines the overall reliability of the product in which the final products are used. Market forces including more functionality in smaller components, no-clean lead-free solder technologies, competitive forces and automated assembly create process challenges. Cleanliness under the bottom terminations must be maintained in harsh environments. Residues under components can attract moisture and lead to leakage currents and the potential for electrochemical migration (...) The purpose of this research study is to evaluate innovative spray and soak methods for removing low residue flux residues and thoroughly rinsing under Bottom Termination and Leadless Components
Technical Library | 2007-02-01 09:57:15.0
The rapid assimilation of Ball Grid Array (BGA) and other Area Array Package technology in the electronics industry is due to the fact that this package type allows for a greater I/O count in a smaller area while maintaining a pitch that allows for ease of manufacture.
Technical Library | 1999-08-05 10:34:17.0
This document defines a set of standard test structures with which to benchmark the electrostatic discharge (ESD) robustness of CMOS technologies. The test structures are intended to be used to evaluate the elements of an integrated circuit in the high current and voltage ranges characteristic of ESD events. Test structures are given for resistors, diodes, MOS devices, interconnects, silicon control rectifiers, and parasitic devices. The document explains the implementation strategy and the method of tabulating ESD robustness for various technologies.
Technical Library | 1999-05-07 08:45:39.0
Fine pitch SMT devices, although certainly not new, present more of an assembly processing challenge than 50 mil pitch devices. In fact it seems that the finer the pitch the more difficult or narrower the process window becomes. Besides the pitch of the leads being less on fine pitch devices narrower pad width on the board is typical. With fine pitch designs the board fabrication process is also stressed in that the strip of mask between the pads is designed narrower, the alignment of the mask to copper becomes more critical
Technical Library | 1999-05-06 11:03:39.0
As microprocessor speeds increase, their power needs rise proportionally. This also puts higher demands on the voltage regulator that feeds the processor chip. In spite of the increased power, the regulator chip tends to remain the same size..
Technical Library | 2009-05-28 18:15:46.0
Considerable effort is ongoing to improve the efficiency and to move towards high-volume manufacturing of photovoltaic cells. Much attention has been focused on developing in-line processes to replace the current batch processes. A critical process to improve the performance of solar wafers is the application of Dopants. The basic requirement for this process is an automated method for applying a very thin, uniform film of Dopant to the silicon wafer as part of an in-line manufacturing process.
Technical Library | 2006-05-13 13:07:53.0
This Excel Spreadsheet calculates the Wave Solder Contact Time automatically with given main Solder Wave width and Conveyor Speed. There is one chart where conveyor speed is expressed in meters/min and in another where it is expressed in feet/minute.
Technical Library | 2008-02-04 12:13:38.0
Engineers are always striving to make a lighter, faster and stronger PCB. In order to achieve their designs, engineers must turn to alternative materials to enhance their designs. There are many materials that allow for thermal, coefficient of thermal expansion (CTE) and rigidity. Many times if a material enables an engineer to have CTE they will have to sacrifice thermal. Currently carbon composite laminates are being used in order to achieve an ideal PCB with thermal, CTE and rigidity with almost no weight premiums.