Technical Library: 2

Deposition of Solder Paste into High Density Cavity Assemblies

Technical Library | 2018-02-28 22:28:30.0

Circuit functional density requirements continue to drive innovative approaches to high performance packaging. Some new approaches include; aggressive space reduction, embedded solutions, and those that offer some form of risk reduction and rework potential are now options that are being explored by customers. Requirements for assembly of these types of packages necessitate the deposition of solder paste and assembly of components into cavities of the substrates to gain z-axis density as well as area functional density. Advances in the fabrication of PWB’s with cavities using newly developed laser micro-fabrication processes along with increased circuit pitch density of 50 micron lines and spaces permit new applications for high performance electronic substrates. First published at SMTA Pan Pacific Symposium

Celestica Corporation

Effect of Silicone Contamination on Assembly Processes

Technical Library | 2013-02-07 17:01:46.0

Silicone contamination is known to have a negative impact on assembly processes such as soldering, adhesive bonding, coating, and wire bonding. In particular, silicone is known to cause de-wetting of materials from surfaces and can result in adhesive failures. There are many sources for silicone contamination with common sources being mold releases or lubricants on manufacturing tools, offgassing during cure of silicone paste adhesives, and residue from pressure sensitive tape. This effort addresses silicone contamination by quantifying adhesive effects under known silicone contaminations. The first step in this effort identified an FT-IR spectroscopic detection limit for surface silicone utilizing the area under the 1263 cm-1 (Si-CH3) absorbance peak as a function of concentration (µg/cm2). The next step was to pre-contaminate surfaces with known concentrations of silicone oil and assess the effects on surface wetting and adhesion. This information will be used to establish guidelines for silicone contamination in different manufacturing areas within Harris Corporation... First published in the 2012 IPC APEX EXPO technical conference proceedings.

Harris Corporation

Development of Halogen Free, Low Loss Copper-Clad Laminates Containing a Novel Phosphonate Oligomer

Technical Library | 2017-08-24 16:53:20.0

With the rapid development of the information industry, increasing attention is being paid to the dielectric performance of base materials including copper-clad laminates (CCL) and prepregs. In addition to the increasingly high performance requirements of CCL's, the present global attention to less toxic products is leading to an increase in the use of halogen-free flame retardants in electronics. (...) This paper introduces a new phosphonate oligomer which can be used as a reactive flame retardant in epoxy based resin systems. Suitable conditions for the complete reaction between the phosphonate oligomer and epoxy resin are described and the resulting halogen-free laminates with improved properties such as low Df, low coefficient of thermal expansion (CTE), high peel strength, and good toughness are presented.

FRX Polymers Inc.

Gold Embrittlement In Lead-Free Solder.

Technical Library | 2014-08-07 15:13:44.0

Gold embrittlement in SnPb solder is a well-known failure mechanism in electronic assembly. To avoid this issue, prior studies have indicated a maximum gold content of three weight percent. This study attempts to provide similar guidance for Pb-free (SAC305) solder. Standard surface mount devices were assembled with SnPb and SAC305 solder onto printed boards with various thicknesses of gold plating. The gold plating included electroless nickel immersion gold (ENIG) and electrolytic gold of 15, 25, 35, and 50 microinches over nickel. These gold thicknesses resulted in weight percentages between 0.4 to 7.0 weight percent.

DfR Solutions

The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish

Technical Library | 2012-10-18 21:58:51.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish.

Agilent Technologies, Inc.

A Life Prediction Model of Multilayered PTH Based on Fatigue Mechanism

Technical Library | 2019-12-26 19:13:52.0

Plated through hole (PTH) plays a critical role in printed circuit board (PCB) reliability. Thermal fatigue deformation of the PTH material is regarded as the primary factor affecting the lifetime of electrical devices. Numerous research efforts have focused on the failure mechanism model of PTH. However, most of the existing models were based on the one-dimensional structure hypothesis without taking the multilayered structure and external pad into consideration.In this paper, the constitutive relation of multilayered PTH is developed to establish the stress equation, and finite element analysis (FEA) is performed to locate the maximum stress and simulate the influence of the material properties. Finally, thermal cycle tests are conducted to verify the accuracy of the life prediction results. This model could be used in fatigue failure portable diagnosis and for life prediction of multilayered PCB.

Beihang University

Investigation of Cutting Quality and Mitigation Methods for Laser Depaneling of Printed Circuit Boards

Technical Library | 2019-09-11 23:33:04.0

There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.

LPKF Laser & Electronics

HALT Testing of Backward Soldered BGAs on a Military Product

Technical Library | 2015-11-19 18:15:07.0

The move to lead free (Pb-free) electronics by the commercial industry has resulted in an increasing number of ball grid array components (BGAs) which are only available with Pb-free solder balls. The reliability of these devices is not well established when assembled using a standard tin-lead (SnPb) solder paste and reflow profile, known as a backward compatible process. Previous studies in processing mixed alloy solder joints have demonstrated the importance of using a reflow temperature high enough to achieve complete mixing of the SnPb solder paste with the Pb-free solder ball. Research has indicated that complete mixing can occur below the melting point of the Pb-free alloy and is dependent on a number of factors including solder ball composition, solder ball to solder paste ratio, and peak reflow times and temperatures. Increasing the lead content in the system enables full mixing of the solder joint with a reduced peak reflow temperature, however, previous research is conflicting regarding the effect that lead percentage has on solder joint reliability in this mixed alloy solder joint.

Lockheed Martin Corporation

Manufacturability & Reliability Challenges with Leadless Near Chip Scale (LNCSP) Packages in Pb-Free Processes

Technical Library | 2011-10-27 18:03:53.0

Leadless, near chip scale packages (LNCSP) like the quad flat pack no lead (QFN) are the fastest growing package types in the electronics industry today. Early LNCSPs were fairly straightforward components with small overall dimensions, a single outer row

DfR Solutions

DOE for Process Validation Involving Numerous Assembly Materials and Test Methods.

Technical Library | 2010-03-18 14:02:03.0

Selecting products that have been qualified by industry standards for use in printed circuit board assembly processes is an accepted best practice. That products which have been qualified, when used in combinations not specifically qualified, may have resultant properties detrimental to assembly function though, is often not adequately understood. Printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks, when qualified per industry standards, are qualified using very specific test methods which may not adequately mimic the assembly process ultimately used.

Trace Laboratories

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