Technical Library | 2012-12-06 17:36:37.0
Inspection of integrated power electronics equals sophisticated test task. X-ray inspection based on 2D / 2.5D principles not utilizable. Full 3D inspection with adapted image capturing and reconstruction is necessary for test task.... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2017-08-10 01:23:22.0
This paper demonstrates the high frequency performance and thermo-mechanical reliability of through vias with 25 μm diameter at 50 μm pitch in 100 μm thin glass substrates. Scaling of through via interconnect diameter and pitch has several electrical performance advantages for high bandwidth 2.5D interposers as well as mm-wave components for 5G modules.
Technical Library | 2021-10-12 18:05:09.0
The remarkable increase in counterfeit parts (a factor of 4 since 2009) [1] is a huge reliability and security concern in various industries ranging from automotive electronics to sensitive military applications increasing the possibility of premature failure in critical systems [2-5]. Counterfeit parts can also incur a great financial loss to legitimate electronics companies [6]. The issue is even more alarming as the counterfeiters use more sophisticated methods making counterfeit detection a much harder task [7-8]. Therefore, it is reasonable to develop more advanced counterfeit detection methods targeting a more efficient detection of sophisticated counterfeited parts.
Technical Library | 2023-11-20 17:30:11.0
Summary for today 1. Electronic component inspection and failure analysis. 2. Component counting and material management. 3. Reverse engineering. 4. Counterfeit detection. 5. Real-time defect verification. 6. Computed tomography (CT) techniques and how to differentiate between 2D, 2.5D, and 3D x-ray inspection. 7. Design for manufacturing (DFM) and design for x-ray inspection (DFXI). 8. Voids, bridging, and head-in-pillow failures in bottom terminated components (BTC). 9. Artificial Intelligence and x-ray inspection
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2016-08-11 15:49:59.0
The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill. A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility.
Technical Library | 2017-09-14 01:21:52.0
The electronics industry is experiencing a renaissance in semiconductor package technology. A growing number of innovative 3D package assembly methodologies have evolved to enable the electronics industry to maximize their products functionality. By integrating multiple die elements within a single package outline, product boards can be made significantly smaller than their forerunners and the shorter interconnect resulting from this effort has contributed to improving both electrical performance and functional capability. (...) This paper outlines both positive and negative aspects of current 3D package innovations and addresses the challenges facing adopters of silicon and glass based interposer fabrication. The material presented will also reference 3D packaging standards and recognize innovative technologies from a number of industry sources, roadmaps and market forecasts.
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