Technical Library: 2020 20.25 (Page 1 of 1)

Reactivity Of No-Clean Flux Residues Trapped Under Bottom Terminated Components

Technical Library | 2017-07-20 15:18:15.0

As electronic devices increase functionality in smaller form factors, there will be limitations, obstacles and challenges to overcome. Advances in component technology can create issues that may have time delayed effects. One such effect is device failure due to soldering residues trapped under bottom terminated components. If the residues trapped under the component termination are active and can be mobilized with moisture, there is the potential for ion mobilization causing current leakage.


Coat-and-Print Patterning of Silver Nanowires for Flexible and Transparent Electronics

Technical Library | 2020-02-19 23:12:55.0

Silver nanowires (Ag NWs) possess excellent optoelectronic properties, which have led to many technology-focused applications of transparent and flexible electronics. Many of these applications require patterning of Ag NWs into desired shapes, for which mask-based and printing-based techniques have been developed and widely used. However, there are still several limitations associated to these techniques. These limitations, such as complicated patterning procedures, limited patterning area, and compromised optical transparency, hamper the efficient fabrication of high-performance Ag NW patterns. Here, we propose a coat-and-print approach for effectively patterning Ag NWs.

Integrated Microwave Packaging Antennas and Circuits Technology (IMPACT) Lab

Approaches to Overcome Nodules and Scratches on Wire Bondable Plating on PCBs

Technical Library | 2020-08-27 01:22:45.0

Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.

Teledyne DALSA

Filling of Microvias and Through Holes by Electrolytic Copper Plating –Current Status and Future Outlook

Technical Library | 2020-03-12 13:10:35.0

The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.


Designing a High Performance Electroless Nickel and Immersion Gold to Maximize Highest Reliability

Technical Library | 2020-11-15 21:22:11.0

The latest highest reliability requirements demand a high performance electroless nickel and immersion gold (HP ENIG). The new IPC specification 4552A has refocused the industry with reference to nickel corrosion. The interpretation of the existing specification, that judges corrosion on 3 levels, is complex and if misinterpreted can lead to phantom failures. An obvious way to avoid any potential misinterpretation is to eradicate any evidence of corrosion completely.


Ultra-Thin Chips For High-Performance Flexible Electronics

Technical Library | 2020-01-15 23:54:34.0

Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics.

Bendable Electronics and Sensing Technologies (BEST)


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