Electronics Forum | Mon Aug 08 16:14:36 EDT 2011 | wmburke
We are building a plasma diagnostic to monitor MHD phenomena in tokamak. As part of the development, we need high-voltage, high-power RF capacitors to tune and match an inductive load. This application is similar to a small induction heater, with t
Electronics Forum | Mon May 15 20:10:27 EDT 2000 | Dave F
David: How about starting with MCMs? IPC docs are: * 2225 - Sectional Design Standard for Organic Multichip Modules (MCM-L) and MCM-L Assemblies * DD-135 - Qualification Testing for Deposited Organic Interlayer Dielectric Materials for Multichip
Electronics Forum | Tue Dec 12 20:37:31 EST 2000 | narasimhan68
Hi, I would like to know the details about getting work permit for US. Presently I am working in India in SMT area over 9 years. If somebody can give some info about will be appreciated for my career growth. narasim
Electronics Forum | Thu Oct 14 18:25:29 EDT 1999 | JAX
Grace, You can get the information you need from IPC. Measuring board warpage is covered in theie 610B manual. It will let you know the what can be reworked and what cannot.
Electronics Forum | Thu May 26 21:07:22 EDT 2005 | KEN
This is caused by cte mis-match. The balls in the corners are short and fat. The balls near the null point are tall and more normalized. I don't remember what the zone settings were... BTU VIP98 BS was probably 22-25 IPM
Electronics Forum | Thu Oct 14 04:28:29 EDT 1999 | Grace Chua
Hi there, I have quite a number of problematic bd due to warpage problem. I would like to know the method on how to measure PCB warpage, thus to decide on the dispositon of these boards. Another question, can these warp bd be rework/fix. Is there
Electronics Forum | Thu Oct 14 20:42:07 EDT 1999 | Jeff Ferry
Grace, As deifned in IPC 7721 Procedure 3.2 Bow and Twist Repair "Bow and twist after soldering shall not exceed 1.5% for through hole PC boards and .75% for surface mount PC boards. The bow and twist shall not be sufficient to cause difficulties d
Electronics Forum | Fri Oct 15 11:05:50 EDT 1999 | Mark Phinney
Earliar we had problems with board warpage, Much of our problem was due to imbalances in the copper on oppisite layers in brief on a 8 layer board the copper on layer 1 should = the copper on layer 8, 2=7, 3=6, 4 = 5. We added copper to some layers t
Electronics Forum | Thu Aug 25 10:32:03 EDT 2005 | davef
IPC-2221A, Generic Standard on Printed Board Design, the base document that covers all generic requirements for printed board design, regardless of materials. From there, the designer can choose the appropriate sectional standard for a specific techn
Electronics Forum | Thu Oct 14 23:01:48 EDT 1999 | Dennis O'Donnell
With loaded boards, warpage can be removed by placing the assembly in a wave solder conveyor pallet as you would if you were going to wave solder the assembly. Place board and fixture in a Blue M forced air oven at 90 C for 30 minutes. Let cool to r
