Technical Library | 2023-01-17 17:27:13.0
Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)
Technical Library | 2019-07-01 10:44:11.0
In the electronics industry of today, companies emphasize better quality, lower cost, and shorter lead time on their products in order to keep up with their competitors. ACI Technologies (ACI) has been utilizing Computer Aided Design (CAD), Computer Aided Manufacturing(CAM), and Computer Aided Engineering (CAE) in its development of advanced electronics systems. CAD utilizes computer systems to assist in the creation, modification, analysis, and optimization of a design [1].
Technical Library | 2019-06-07 14:49:54.0
ACI Technologies was contacted in regards to poor solder joint reliability. The customer submitted an assembly that was exhibiting intermittent opens at multiple locations on a ball grid array (BGA) component. The assembly’s functionality did not survive international shipping, essentially shock and vibration failures, immediately making the quality of the solder joints suspect. The customer was asked about the contract manufacturer and the reflow oven profile as well as the solder paste and surface finish used. The ACI engineering staff evaluated the contract manufacturer’s technique and determined that they were competent in the methods they used for placing thermocouples in the proper locations and developing the reflow oven profile. The surface finish was unusual, but not unheard of, in that it was hard gold over hard nickel, rather than electroless nickel immersion gold (ENIG). The customer was able to supply boundary scan testing data which showed a diagonal row of troublesome BGA pins.
Technical Library | 2020-04-01 14:24:56.0
It happens much too often; manufacturing engineers are brought into a NEW product design phase at the very end of a design and are asked to provide input that should have been provided much earlier. One needs to understand how the circuit board design and quality of the manufacturing process not only effects assembly yield and product reliability, but how it could also affect the results of any testing that is done to circuit packs during prototyping. It is important that any circuit pack (including prototypes) that will be used in reliability, performance and functional testing be designed with the proper features and assembled with a manufacturing process that has been developed to produce a high-quality assembly. If not, the results of any testing might not represent the actual characteristics of the design and provide miss-guidance to future changes.
Technical Library | 2023-03-13 19:35:47.0
Translational Research in Additive Manufacturing at GTMI * Additive manufacturing/3D printing process and equipment development (e.g., metal, polymer and composites part manufacturing) * Computational modeling and simulation of additive manufacturing/printed electronics processes * Advanced materials development for additive manufacturing/printed electronics * Application development and demonstration of additive manufacturing/printed electronics
Technical Library | 1999-05-07 10:16:31.0
This paper will describe practical aspects of a redundancy implementation on a high-volume cache memory product. Topics covered include various aspects of redundancy from a design and product engineering perspective; and present test development methods for future product implementations.
Technical Library | 2020-03-12 13:10:35.0
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.
Technical Library | 1999-05-06 14:48:20.0
This paper describes manufacturing operations design and analysis at Intel. The complexities and forces of both the market and the manufacturing process combine to make the development of improved semiconductor fabrication manufacturing strategies (like lot dispatching, micro and macro scheduling policies, labor utilization, layout, etc.) particularly important...
Technical Library | 2018-11-14 21:43:14.0
Status of flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill will be reviewed in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. Finally, the competition on flip chip technology will be briefly mentioned.
Technical Library | 1999-05-07 10:13:38.0
This paper will review the device physics governing the operation of the industry standard ETOX™ flash memory cell and show how it is ideally suited for multiple bit per cell storage, through its storage of electrons on an electrically isolated floating gate and through its direct access to the memory cell.
