Technical Library | 2021-02-20 00:55:47.0
Customers must be able to rely on accurate humidity indication as an assurance of SMD quality and fitness for processing and use. Without it, they might accept SMDs from suppliers that have already been irreparably damaged by moisture during storage or transit. Or, they might approve for processing SMDs that have been improperly or insufficiently heat-dried. Beyond the processing questions, there are financial questions: Where did the dry pack problems originate and who--supplier, customer, shipper--is financially responsible for the damaged SMDs? In response, Clariant, the originator of the color change humidity indicator card, and a member of the JEDEC's Subcommittee 14.1, "Reliability and Test Methods for Packaged Devices," created a new "non-reversible" halogen and cobalt dichloride free humidity indicator card. This HIC combines two reversible indicators (5% and 10%) with a new non-reversible (60% RH) indicator spot. (Figure 1) The 5% and 10% reversible spots work the way similar indicators do: they change color from blue (dry), to lavender, to pink (wet) to indicate humidity exposure at the indicated levels. If humidity levels drop, they will gradually revert back to blue.
Technical Library | 2023-01-10 20:03:37.0
Since the IPC-4552 rev A for ENIG was introduced there have been many requests for clarification of acceptable and unacceptable levels of nickel corrosion. This paper attempts to further clarify the effects of nickel corrosion on solder wetting balance test results and the resultant intermetallic formed. The study will attempt to produce level 1, level 2, and level 3 corrosion as denoted by IPC-4552 rev A and tabulate wetting balance results and congruity of intermetallic formed.
Technical Library | 2015-06-04 19:10:47.0
Integrators and designers of high-reliability systems exert little or no control over component-level plating processes that affect the propensity for tin whiskering. Challenges of how to assure long-term reliability, while continuing to use COTS parts plated with pure tin, continue to arise. An integrated, quantitative, standardized methodology is proposed whereby mitigation levels can be selected that are appropriate for specific applications of pure tin for given end-uses. A system of hardware end-use classification is proposed, together with recommended appropriate risk mitigation approaches. An updated version of the application-specific risk assessment algorithm is presented together with recommended thresholds for acceptability within the context of the hardware classifications.
Technical Library | 2007-11-29 17:20:31.0
Programs have been developed to predict the expected yield of flip chip assemblies, based on substrate design and the statistics of actual manufactured boards, as well as placement machine accuracy, variations in bump sizes, and possible substrate warpage. These predictions and the trends they reveal can be used to direct changes in design so that defect levels will fall below the acceptable limits. Shapes of joints are calculated analytically, or when this is not possible, numerically by means of a public domain program called Surface Evolver. The method is illustrated with an example involving the substrate for a flip chip BGA.
Technical Library | 2012-08-30 21:24:29.0
This paper provides definitions of the different voiding types encountered in Gull Wing solder joint geometries. It further provides corresponding reliability data that support some level of inclusion voiding in these solder joints and identifies the final criteria being applied for certain IBM Server applications. Such acceptance criteria can be applied using various available x-ray inspection techniques on a production or sample basis. The bulk of supporting data to date has been gathered through RoHS server exempt SnPb eutectic soldering operations but it is expected to provide a reasonable baseline for pending Pb-free solder applications.
Technical Library | 2020-11-04 17:57:41.0
Residues present on circuit boards can cause leakage currents if not controlled and monitored. How "Clean is Clean" is neither easy nor cheap to determine. Most OEMs use analytical methods to assess the risk of harmful residues. The levels that can be associated with clean or dirty are typically determined based on the exposed environment where the part will be deployed. What is acceptably clean for one segment of the industry may be unacceptable for more demanding segments. As circuit assemblies increase in density, understanding cleanliness data becomes more challenging. The risk of premature failure or improper function is typically site specific. The problem is that most do not know how to measure or define cleanliness nor can they recognize process problems related to residues. A new site specific method has been designed to run performance qualifications on boards built with specific soldering materials, reflow settings and cleaning methods. High impedance measurements are performed on break off coupons designed with components geometries used to build the assembly. The test method provides a gauge of potential contamination sources coming from the assembly process that can contribute to electrochemical migration.
Technical Library | 2022-10-31 17:25:37.0
Mixed formulation solder alloys refer to specific combinations of Sn-37Pb and SAC305 (96.5Sn–3.0Ag–0.5Cu). They present a solution for the interim period before Pb-free electronic assemblies are universally accepted. In this work, the surfaces of mixed formulation solder alloys have been studied by in situ and real-time Auger electron spectroscopy as a function of temperature as the alloys are raised above the melting point. With increasing temperature, there is a growing fraction of low-level, bulk contaminants that segregate to the alloy surfaces. In particular, the amount of surface C is nearly _50–60 at. % C at the melting point. The segregating impurities inhibit solderability by providing a blocking layer to reaction between the alloy and substrate. A similar phenomenon has been observed over a wide range of (SAC and non-SAC) alloys synthesized by a variety of techniques. That solder alloy surfaces at melting have a radically different composition from the bulk uncovers a key variable that helps to explain the wide variability in contact angles reported in previous studies of wetting and adhesion. VC 2011 American Vacuum Society. [DOI: 10.1116/1.3584821]
Technical Library | 2020-10-14 14:33:36.0
Epoxy based adhesives are prevalent interface materials for all levels of electronic packaging. One reason for their widespread success is their ability to accept fillers. Fillers allow the adhesive formulator to tailor the electrical and thermal properties of a given epoxy. Silver flake allow the adhesive to be both electrically conductive and thermally conductive. For potting applications, heat sinking, and general encapsulation where high electrical isolation is required, aluminum oxide has been the filler of choice. Today, advanced Boron Nitride filled epoxies challenge alternative thermal interface materials like silicones, greases, tapes, or pads. The paper discusses key attributes for designing and formulating advanced thermally conductive epoxies. Comparisons to other common fillers used in packaging are made. The filler size, shape and distribution, as well as concentration in the resin, will determine the adhesive viscosity and rheology. Correlation's between Thermal Resistance calculations and adhesive viscosity are made. Examples are shown that determination of thermal conductivity values in "bulk" form, do not translate into actual package thermal resistance. Four commercially available thermally conductive adhesives were obtained for the study. Adhesives were screened by shear strength measurements, Thermal Cycling ( -55 °C to 125 °C ) Resistance, and damp heat ( 85 °C / 85 %RH ) resistance. The results indicate that low modulus Boron Nitride filled epoxies are superior in formulation and design. Careful selection of stress relief agents, filler morphology, and concentration levels are critical choices the skilled formulator must make. The advantages and limitations of each are discussed and demonstrated.
Technical Library | 2021-11-26 14:34:07.0
The use of desiccant bags filled with Silica Sand and or Clay beads used in conjunction with a Moisture Barrier Bag to control moisture for storage of printed circuit boards has long been an accepted practice and standard from both JEDEC and IPC organizations. Additionally, the use heated ovens for baking off moisture using the evaporation process has also been a long#2;standing practice from these organizations. This paper on alternative drying methods will be accompanied by completed independent, unbiased tests conducted by Vinny Nguyen, an engineering student (now graduated) from San Jose State University. The accompanied paper will examine the performance levels of different technologies of desiccant bags to control moisture in enclosed spaces. The tests and equipment set were reviewed by an engineer and consultant to the Lockheed Martin Aerospace Division and the IPC - TM-650 2.6.28 test method was review by engineer from pSemi. The tests were designed to mimic performance tests outlined in Mil Spec 3464, which both IPC and JEDEC have adopted for their respective standards. The test examined variables including absorption capacity rates, weight gain and release of moisture back into the enclosed area. The presentation will also address and highlight: • Similarities of PCBs and Heavy Equipment as it applies to Inspections, Causes of Failure, Types of Corrosion and Moisture Collection Points. • Performance Attributes of Different Desiccant Technologies as it applies to shape, texture, change outs, labeling and regeneration. • Venn Diagram of Electromechanical Failure with the circles 1. Current 2. Contamination 3. Humidity Presentation Available
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