Technical Library | 2016-05-30 22:24:00.0
As a part of series of studies on X-Ray inspection technology to quantify solder defects in BGA balls, we have conducted inspection of 3 level POP package by using a new AXI that capable of 3D-CT imaging. The new results are compared with the results of earlier AXI measurements. It is found that 3D measurements offer better defect inspection quality, lower false call and escapes.
Technical Library | 2021-01-28 01:55:00.0
Printed circuit board surface finishes are a topic of constant discussion as environmental influences, such as the Restriction of Hazardous Substances (RoHS) Directive or technology challenges, such as flip chip and 01005 passive components, initiate technology changes. These factors drive the need for greater control of processing characteristics like coplanarity and solderability, which influence the selection of surface finishes and impact costs as well as process robustness and integrity. The ideal printed circuit board finish would have good solderability, long shelf life, ease of fabrication/processing, robust environmental performance and provide dual soldering/wirebonding capabilities; unfortunately no single industry surface finish possesses all of these traits. The selection of a printed circuit board surface finish is ultimately a series of compromises for a given application.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
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