Electronics Forum | Tue Jul 18 16:49:49 EDT 2023 | mahasg
Hello All, I am PhD student at polytechnique Montreal. We have a CQFP44 packages and Dies of 51um pad pitch (22nm FDSOI tech) that I need to bond myself at the university using ASM Eagle Xtreme gold wire bonder in the university. we need to perform b
Electronics Forum | Wed Mar 29 18:17:16 EST 2000 | David
Does anybody out there have experience building electronics assemblies with DCA (Direct Chip Attach - bare die onto PCB) and wire bonding? - What Die Bonder/Dispensing Machines are recommended? - What brand conductive epoxy were used to attach die?
Electronics Forum | Tue Jan 09 22:04:48 EST 2007 | Guest
Set Up Guy, I am not sure if the COB you are refering to means Circuit on Board . If yes, this process also include SMT . Package is a combination of some passive components and bare die. Passives are normally attached thru SMT using solder te
Electronics Forum | Tue Nov 05 06:51:59 EST 2002 | V.RAMANAND KINI
Hi, This is a widely discussed subject and since you have asked a brief explanation, I assume, you are a business man or a top executive in the company venturing in to COB. I waited to see if someone replies to you. May be it is a very old subject
Electronics Forum | Wed Jul 15 08:36:41 EDT 2020 | dproldan
Using a X-Rays machine, we have noticed that one component we are using has the silicon die bonded at an angle in the package. Have you ever seen something like this? I'm not sure if it's intentional or a manufacturing error.
Electronics Forum | Wed Aug 28 10:16:12 EDT 2002 | Jim M.
Sam We install a lot of die in the SMT room using same process as SMT parts.Water soluble solder paste is used for attachment of die to ceramic and boards. Biggest problem i found is the adjustment from installing the die in the bonding area. The t
Electronics Forum | Fri Nov 27 02:09:50 EST 1998 | Chi-Ting Chen
| | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is c
Electronics Forum | Fri Nov 27 02:11:17 EST 1998 | Chi-Ting Chen
| | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is c
Electronics Forum | Thu Sep 19 02:45:33 EDT 2002 | bugsjoe
Thank you ur reply Dave. Let me explain our COB workflow: 1. unpack PCB (FR4,LPI,HASL)(the thickness of gold and nickel we can't be find)(No SMT before) 2. clean the pcb by rubber 3. blow the pcb by di-ionic gun 4. attach die by adhesive gel 5. cure
Electronics Forum | Fri Nov 27 08:07:50 EST 1998 | Earl Moon
| | | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is