Technical Library: bare and board and loader (Page 1 of 3)

Combination of Spray and Soak Improves Cleaning under Bottom Terminations

Technical Library | 2014-10-23 18:10:10.0

The functional reliability of electronic circuits determines the overall reliability of the product in which the final products are used. Market forces including more functionality in smaller components, no-clean lead-free solder technologies, competitive forces and automated assembly create process challenges. Cleanliness under the bottom terminations must be maintained in harsh environments. Residues under components can attract moisture and lead to leakage currents and the potential for electrochemical migration (...) The purpose of this research study is to evaluate innovative spray and soak methods for removing low residue flux residues and thoroughly rinsing under Bottom Termination and Leadless Components

KYZEN Corporation

High Performance Multilayer PCBs Design and Manufacturability

Technical Library | 2013-10-31 17:36:41.0

Multilayer printed circuit boards (PCBs) that utilize high performance materials are inherently far more challenging for a fabricator to build, due to significant material property differences over standard epoxy glass FR4. These unique material characteristics often require higher processing temperatures, special surface treatments (to aid in hole and surface plating), they possess different expansion properties, making layer-to-layer registration more difficult to control, and require many other unique considerations.

Spectrum Integrity, Inc.

Cleanliness of Stencils and Cleaned Misprinted Circuit Boards

Technical Library | 2010-09-09 16:44:48.0

The effectiveness of cleaning stencils and misprinted/dirty printed circuit boards can be effectively monitored. This can be done by washing known clean circuit boards and then checking to see if they have stayed clean as a result of the washing process.

Research In Motion

Microspring Characterization and Flip-Chip Assembly Reliability

Technical Library | 2014-05-29 13:48:14.0

Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance ( 30 μm) in dense 2-D arrays (180 ~ 180-µm pitch). Mechanical characterization shows that individual springs operate at approximately 150-µN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules.

Institute of Electrical and Electronics Engineers (IEEE)

Print Performance Studies Comparing Electroform and Laser-Cut Stencils

Technical Library | 2015-11-05 15:09:27.0

There has been recent activity and interest in Laser-Cut Electroform blank foils as an alternative to normal Electroform stencils. The present study will investigate and compare the print performance in terms of % paste transfer as well the dispersion in paste transfer volume for a variety of Electroform and Laser-Cut stencils with and without post processing treatments. Side wall quality will also be investigated in detail. A Jabil solder paste qualification test board will be used as the PCB test vehicle.

Photo Stencil LLC

New Methods of Testing PCB Traces Capacity and Fusing

Technical Library | 2011-11-25 16:07:47.0

The article presents virtual and real investigations related to current capacity and fusing of PCB traces in high power applications and is based on a scientific paper delivered by authors at SIITME 2010 in Romania. The reason of performing the research a

UPB-CETTI University of Bucharest, Center for Technological Electronics and Interconnection Techniques

Solar Panel Design Decision and General Information Sheet

Technical Library | 2014-04-10 18:04:04.0

This paper is meant to be a guide and a reference to new and old members alike who wish to know about, understand, and improve on the decisions made and processes implemented to build the current solar panels. The following paragraphs in the introduction will lay out background information on solar panels and cube satellites. This entire document was written with the idea that the reader will be able to follow the decisions made to construct the solar panels and then with this knowledge find areas of the project for improvement.

iSAT Group

Printed Circuit Board Tracking with RFID: Speed, Efficiency and Productivity Made Simple.

Technical Library | 2008-05-07 17:54:58.0

Tracking goods through manufacturing was originally accomplished with pencil, paper and human input. Barcodes introduced an automated, machine-readable tracking mechanism that streamlined all types of manufacturing. But modern printed circuit board (PCB) assemblies are running into limitations because of barcode labels. And though barcodes and RFID tags will co-exist, the relatively large barcode labels have to find increasingly scarce real estate on high density boards.

Texas Instruments

Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

Technical Library | 2018-08-22 14:05:42.0

Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5-µm lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than 15 × 15 mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances.

Institute of Electrical and Electronics Engineers (IEEE)

Press Fit Technology Roadmap and Control Parameters for a High Performance Process

Technical Library | 2016-10-27 16:24:23.0

Press-fit technology is a proven and widely used and accepted interconnection method for joining electronics assemblies. Printed Circuit Board Assembly Systems and typical functional subassemblies are connected through press-fit connectors. The Press-Fit Compliant Pin is a proven interconnect termination to reliably provide electrical and mechanical connections from a Printed Circuit Board to an Electrical Connector. Electrical Connectors are then interconnected together providing board to board electrical and mechanical inter-connection. Press-Fit Compliant Pins are housed within Connectors and used on Backplanes, Mid-planes and Daughter Card Printed Circuit Board Assemblies. High reliability OEM (Original Equipment Manufacturer) computer designs continue to use press-fit connections to overcome challenges associated with soldering, rework, thermal cycles, installation and repair. This paper investigates the technical roadmap for press fit technology, putting special attention to main characteristics such, placement and insertion, inspection, repair, pin design trends, challenges and solutions. Critical process control parameters within an assembly manufacturing are highlighted.

Flex (Flextronics International)

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