Technical Library | 2010-08-26 19:45:44.0
The advantages of the Compression Mount Technology (CMT) when using AdvancedTCA and MicroTCA connectors.
Technical Library | 1999-05-06 14:48:20.0
This paper describes manufacturing operations design and analysis at Intel. The complexities and forces of both the market and the manufacturing process combine to make the development of improved semiconductor fabrication manufacturing strategies (like lot dispatching, micro and macro scheduling policies, labor utilization, layout, etc.) particularly important...
Technical Library | 2007-11-01 17:16:07.0
This paper discusses micro-filled epoxy-based conducting adhesives modified with nanoparticles, conducting polymers, and low melting point (LMP) fillers for z-axis interconnections, especially as they relate to package level fabrication, integration,
Technical Library | 2013-08-07 21:52:15.0
PCB architectures have continued their steep trend toward greater complexities and higher component densities. For quality control managers and test technicians, the consequence is significant. Their ability to electrically test these products is compounded with each new generation. Probe access to high density boards loaded with micro BGAs using a conventional in-circuit (bed-of-nails) test system is greatly reduced. The challenges and complexity of creating a comprehensive functional test program have all but assured that functional test will not fill the widening gap. This explains why sales of automated-optical and automated X-ray inspection (AOI and AXI) equipment have dramatically risen...
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2009-05-07 23:23:00.0
Thermal fatigue has been one of the most serious problems for solder joint reliability. Thermo-mechanical fatigue failure is considered to be closely related to micro-structural coarsening (grain/phase growth). Factors that influence the phase growth are studied and measurement methods are discussed, including the preparation of the eutectic solder sample for phase size measurement. Three categories of models used to predict grain growth in polycrystalline materials are presented. Finally, phase growth in solder during high temperature aging and temperature cycling and its use as a damage correlation factor are discussed.
Technical Library | 2016-08-24 06:15:35.0
From consumer electronics to systems control, automotive technology to aviation and aerospace – today, electronics are absolutely essential in many sectors. They increasingly replace mechanical components, eliminating wear and tear and thereby extending the service life. What is easily forgotten in this regard is that electronics are also subject to the laws of mechanics. Mechanical test equipment is crucial to test components for the secure hold of welded, soldered or adhesive bonds. A new, mechanically intricate test probe with universal clamping jaws, that can even grasp the individual bonding wires, is in line with the trend toward ever smaller components. Serving as an actuator for these is a micro drive that can be precisely controlled using a miniaturised motion controller to relieve the control unit in the test device.
Technical Library | 2022-06-27 16:50:26.0
Electronics industry is one of the fastest evolving, innovative, and most competitive industries. In order to meet the high consumption demands on electronics components, quality standards of the products must be well-maintained. Automatic optical inspection (AOI) is one of the non-destructive techniques used in quality inspection of various products. This technique is considered robust and can replace human inspectors who are subjected to dull and fatigue in performing inspection tasks. A fully automated optical inspection system consists of hardware and software setups. Hardware setup include image sensor and illumination settings and is responsible to acquire the digital image, while the software part implements an inspection algorithm to extract the features of the acquired images and classify them into defected and non-defected based on the user requirements. A sorting mechanism can be used to separate the defective products from the good ones. This article provides a comprehensive review of the various AOI systems used in electronics, micro-electronics, and opto-electronics industries. In this review the defects of the commonly inspected electronic components, such as semiconductor wafers, flat panel displays, printed circuit boards and light emitting diodes, are first explained. Hardware setups used in acquiring images are then discussed in terms of the camera and lighting source selection and configuration. The inspection algorithms used for detecting the defects in the electronic components are discussed in terms of the preprocessing, feature extraction and classification tools used for this purpose. Recent articles that used deep learning algorithms are also reviewed. The article concludes by highlighting the current trends and possible future research directions.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
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