Technical Library: clara (Page 1 of 3)

Validity of the IPC R.O.S.E. Method 2.3.25 Researched

Technical Library | 2010-06-10 21:01:48.0

This paper researches the effectiveness of the R.O.S.E. cleanliness testing process for dissolving and measuring ionic contaminants from boards soldered with no-clean and lead-free flux technologies.

KYZEN Corporation

New High-Speed 3D Surface Imaging Technology in Electronics Manufacturing Applications

Technical Library | 2020-03-26 14:55:29.0

This paper introduces line confocal technology that was recently developed to characterize 3D features of various surface and material types at sub-micron resolution. It enables automatic microtopographic 3D imaging of challenging objects that are difficult or impossible to scan with traditional methods, such as machine vision or laser triangulation.Examples of well-suited applications for line confocal technology include glossy, mirror-like, transparent and multi-layered surfaces made of metals (connector pins, conductor traces, solder bumps etc.), polymers (adhesives, enclosures, coatings, etc.), ceramics (components, substrates, etc.) and glass (display panels, etc.). Line confocal sensors operate at high speed and can be used to scan fast-moving surfaces in real-time as well as stationary product samples in the laboratory. The operational principle of the line confocal method and its strengths and limitations are discussed.Three metrology applications for the technology in electronics product manufacturing are examined: 1. 3D imaging of etched PCBs for micro-etched copper surface roughness and cross-sectional profile and width of etched traces/pads. 2. Thickness, width and surface roughness measurement of conductive ink features and substrates in printed electronics applications. 3. 3D imaging of adhesive dots and lines for shape, dimensions and volume in PCB and product assembly applications.

FocalSpec, Inc.

Solving the ENIG Black Pad Problem: An ITRI Report on Round 2

Technical Library | 2013-01-17 15:37:21.0

A problem exists with electroless nickel / immersion gold (ENIG) surface finish on some pads, on some boards, that causes the solder joint to separate from the nickel surface, causing an open. The solder has wet and dissolved the gold. A weak tin to nickel intermetallic bond initially occurs, but the intermetallic bond cracks and separates when put under stress. Since the electroless nickel / immersion gold finish performs satisfactory in most applications, there had to be some area within the current chemistry process window that was satisfactory. The problem has been described as a 'BGA Black Pad Problem' or by HP as an 'Interfacial Fracture of BGA Packages…'[1]. A 24 variable experiment using three different chemistries was conducted during the ITRI (Interconnect Technology Research Institute) ENIG Project, Round 1, to investigate what process parameters of the chemical matrix were potentially satisfactory to use and which process parameters of the chemical matrix need to be avoided. The ITRI ENIG Project has completed Round 1 of testing and is now in the process of Round 2 TV (Test Vehicle) build.

Celestica Corporation

Nike's Software Architecture and Infrastructure: Enabling Integrated Solutions for Gigahertz Designs

Technical Library | 1999-05-06 14:03:04.0

This paper describes how Nike’s innovative architecture addresses the expanding requirements of Intel’s next-generation processor designs while enabling a design environment that is more productive than one built with the previous tool generation.

Intel Corporation

Intel StrataFlash™ Memory Technology Overview

Technical Library | 1999-05-07 10:11:55.0

The Intel StrataFlashTM memory technology represents a cost breakthrough for flash memory devices by enabling the storage of two bits of data in a single flash memory transistor. This paper will discuss the evolution of the two bit/cell technology from conception to production.

Intel Corporation

Total Loss: How to Qualify Circuit Boards

Technical Library | 2011-05-12 19:04:05.0

We clarify the role of signal loss measurements, aka Total Loss, in specifying and qualifying circuit board materials for high-speed electronic design. We then demonstrate the NIST Multiline measurement technique in particular by characterizing test line

Connected Community Networks, Inc.

Good Product Quality Comes From Good Design for Test Strategies

Technical Library | 2015-12-17 17:24:17.0

Product quality can be improved through proper application of design for test (DFT) strategies. With today's shrinking product sizes and increasing functionality, it is difficult to get good test coverage of loaded printed circuit boards due to the loss of test access. Advances in test techniques, such as boundary scan, help to recover this loss of test coverage. However, many of these test techniques need to be designed into the product to be effective.This paper will discuss how to maximize the benefits of boundary scan test, including specific examples of how designers should select the right component, connect multiple boundary scan components in chains, add test access to the boundary scan TAP ports, etc. A discussion of DFT guidelines for PCB layout designers is also included. Finally, this paper will include a description of some advanced test methods used in in-circuit tests, such as vectorless test and special probing methods, which are implemented to improve test coverage on printed circuit boards with limited test access.

Agilent Technologies, Inc.

High Frequency Dk and Df Test Methods Comparison High Density Packaging User Group (HDP) Project

Technical Library | 2019-02-06 22:02:08.0

The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods, with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired, testing a variety of laminate materials (standard volume production with UL approval, low loss, and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified, as well as possible correlations or relationships among these higher speed test methods.

Oracle Corporation

Illinois-Intel Multithreading Library: Multithreading Support for Intel Architecture Based Multiprocessor Systems

Technical Library | 1999-05-07 10:04:13.0

Powerful desktop multiprocessor systems based on the Intel Architecture (iA) offer a formidable alternative to traditional scientific/engineering workstations for commercial application developers at an attractive costperformance ratio. However, the lack of adequate compiler and runtime library support for multithreading and parallel processing on Windows NT* makes it difficult or impossible to fully exploit the performance advantage of these multiprocessor systems. In this paper we describe the design, development, and initial performance results of the Illinois-Intel Multithreading Library (IML), which aims at providing an efficient and powerful (in terms of types of parallelism it supports) API for multithreaded application developers.

Intel Corporation

Round Robin of High Frequency Test Methods by IPC-D24C Task Group

Technical Library | 2017-06-29 16:39:30.0

Currently there is no industry standard test method for measuring dielectric properties of circuit board materials at frequencies greater than about 10 GHz. Various materials vendors and test labs take different approaches to determine these properties. It is common for these different approaches to yield varying values of key properties like permittivity and loss tangent. The D-24C Task Group of IPC has developed this round robin program to assess these various methods from the "bottom up" to determine if standardized methods can be agreed upon to provide the industry with more accurate and valid characteristics of dielectrics used in high-frequency and high-speed applications.


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