Electronics Forum | Fri Jun 06 18:44:26 EDT 2003 | davef
No, no. It's koscher to have thermal planes. You just need to: * Work with your fabricator to keep the layup balanced. * Relieve the plane so that it doesn't cause assembly problems. While probably not directly for your part, it gives a starting p
Electronics Forum | Sat Jan 30 16:42:32 EST 2016 | davef
Many board fabs help their customer understand the importance of copper balance. Copper balance * http://www.multi-circuit-boards.eu/en/pcb-design-aid/copper-balance.html * http://electronics.stackexchange.com/questions/85633/what-is-copper-thiev
Electronics Forum | Thu Jun 24 15:33:56 EDT 2010 | davef
Our best suggestion - get the copper balanced and if possible go to higher Tg materials.
Electronics Forum | Tue Jun 20 06:47:53 EDT 2006 | Julien VITTU (STMicro)
hung copper balance is really critical in your case. in the same configuration we have specified less than 5% copper variation between top and bottom layer if you keep this rule, assembly will be ok, otherwise you will get a terrible warpage after
Electronics Forum | Mon Mar 13 22:29:50 EST 2006 | davef
Warp depends on: * How close the board gets to its Tg during the reflow cycle (the closer you get to the Tg the worse the warp gets) * Amount of copper on each side and the balance between the two * Thickness of the board * Overall length x width * T
Electronics Forum | Mon Jul 25 08:56:47 EDT 2005 | russ
In addition to Daves comments. You might want to look at the layer construction to see if the copper is balanced throughout the board.
Electronics Forum | Fri Jul 13 04:58:01 EDT 2007 | pavel_murtishev
Good afternoon, Heating/Cooling rates contribute to warpage most of all. Try to tweak you profile so that heating/cooling rate would be minimized. Try to switch cooling blowers off maintaining required peak/TAL. Check copper balance for this PWB, by
Electronics Forum | Wed Aug 03 21:20:09 EDT 2005 | Ken
CTE mismatch. X, Y, Z all expand at different rates. Cooling or heating rates will not change this CTE mismatch. Layer counts, power plane ballance, equal run lengths in x-y and copper balance all contribute. Have your supplier evaluate your s
Electronics Forum | Tue Apr 29 11:18:16 EDT 2008 | julienvittu
basically your problems come from the copper balance top and bottom side we are using substrate down to 0.18mm (semiconductor industry/ Bga package / SIp business) you have to respect 5% difference maximum between Top and bottom side otherwise you
Electronics Forum | Fri Jun 25 15:04:39 EDT 2010 | siddharth
Thanks for you suggestions, guys. davef, I am gonna get with my PCB suppliers and talk to them about copper balancing and checking the Tg of the materials they use. SC, I am working towards designing wave pallets for my boards and try your suggesti
