Technical Library | 2019-06-04 10:19:46.0
Interconnection technology relies very heavily on the ability of the conductors on a printed wiring assembly to maintain reliable signal integrity. Harsh environmental factors can precipitate a loss of conductivity due to oxidation and corrosion. Connections are typically soldered or inserted using pressure fitted connectors to obtain enough surface contact to meet the electrical conductivity requirements. In pressure contacts, surface integrity is especially critical where the abrasive effects of retraction and insertion can wear off the metallic finish from the contact area. This can expose the underlying copper or nickel and lead to increased resistance at the contact points. These types of conductors are frequently found in card edge connectors where the terminations are plated with a layer of nickel and gold (frequently referred to as gold fingers). A hard gold is typically used containing very small amounts of nickel and cobalt to increase the wear resistance.
Technical Library | 2020-03-12 13:10:35.0
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.
Technical Library | 2020-07-22 19:39:05.0
The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures. Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable. The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for a reliable PWB. Minimum copper wrap plating thickness has become an even a bigger concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design. PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching. The companies started a project to study the relationship between Copper wrap plating thickness and via reliability. The project had two phases. This paper will present findings from both Phase 1 and Phase 2.
Technical Library | 2016-01-07 19:13:23.0
The purpose of this study is to investigate the effect of plasma surface modification to improve adhesion strength between polytetrafluoroethylene (PTFE) and electroless copper plating. PTFE is widely used in many industries because of its unique electrical, thermal, and mechanical characteristics. However, because of its low surface energy, it is difficult to acquire enough adhesion strength between PTFE and other substances without surface modification. Plasma is well known as one of the surface modification techniques that improve adhesion strength.
Technical Library | 2015-11-12 19:04:51.0
In order to provide the functionality in today’s electronics, printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces, this means no nodules, no pits, and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However, the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble, phosphorized, copper anodes introduce particulate and limits the ability to control plating distribution.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2016-07-21 18:16:06.0
Achieving optimum high-frequency printed-circuit-board (PCB) performance is not simply a matter of specifying the best possible PCB material, but can be significantly impacted by PCB fabrication practices. In addition to appropriate circuit materials and circuit design configurations to meet target performance goals, a number of PCB material-related issues can affect final performance, including the use of soldermask, the PCB copper plating thickness, the conductor trapezoidal effect, and plating finish; understanding the effects of these material issues can help when fabricating high-frequency circuits for the best possible electrical performance.
Technical Library | 2020-07-15 18:29:34.0
In the early 2000s the first fine-pitch ball grid array devices became popular with designers looking to pack as much horsepower into as small a space as possible. "Smaller is better" became the rule and with that the mechanical drilling world became severely impacted by available drill bit sizes, aspect ratios, and plating methodologies. First of all, the diameter of the drill needed to be in the 0.006" or smaller range due to the reduction of pad size and spacing pitch. Secondly, the aspect ratio (depth to diameter) became limited by drill flute length, positional accuracy, rigidity of the tools (to prevent breakage), and the throwing power of acid copper plating systems. And lastly, the plating needed to close up the hole as much as possible, which led to problems with voiding, incomplete fill, and gas/solution entrapment.
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.