Technical Library: cs 400 (Page 1 of 2)

Miniaturizing IoT Designs

Technical Library | 2016-11-23 00:26:50.0

As we wirelessly connect more and more devices to the Internet, electronics engineers face several challenges, including how to package a radio transmitter into their existing device real estate and how to make increasingly smaller devices. They’re also striving to meet consumer demand for Internet of Things (IoT) products that are ergonomically easy to use and unobtrusive to the environment. This whitepaper explores the challenges that come with designing connected devices into increasingly smaller products, specifically antenna integration, and how system-inpackage modules can help.

Silicon Labs

A Study of Lead-Free Solder Alloys

Technical Library | 1999-05-09 14:14:51.0

With the ongoing concern regarding environmental pollutants, Iead is being targeted in the electronic assembly arena. This paper highlights lead-free solders and the different combinations of elemental makeups.

AIM Solder

SMT Under Stencil Wiper Rolls

Technical Library | 2019-06-03 21:07:34.0

The objective of this White Paper is to provide users of the above products in the electronics industry a clear understanding of the different types of stencil cleaning paper/fabrics that are currently available. Fine pitch applications are more the norm now and so the performance of stencil cleaning rolls is more critical than ever before. This White Paper will give solder paste stencil printing engineers and purchasing professionals an insight into the main products on the market, thereby enabling them to make informed decisions.

Swiftmode Malaysia (Penang) Sdn Bhd

Effect of Cu–Sn intermetallic Compound Reactions on the Kirkendall Void Growth Characteristics in Cu/Sn/Cu Microbumps

Technical Library | 2014-07-02 16:46:09.0

Growth behaviors of intermetallic compounds (IMCs) and Kirkendall voids in Cu/Sn/Cu microbump were systematically investigated by an in-situ scanning electron microscope observation. Cu–Sn IMC total thickness increased linearly with the square root of the annealing time for 600 h at 150°C, which could be separated as first and second IMC growth steps. Our results showed that the growth behavior of the first void matched the growth behavior of second Cu6Sn5, and that the growth behavior of the second void matched that of the second Cu3Sn. It could be confirmed that double-layer Kirkendall voids growth kinetics were closely related to the Cu–Sn IMC growth mechanism in the Cu/Sn/Cu microbump, which could seriously deteriorate the mechanical and electrical reliabilities of the fine-pitch microbump systems

Nepes Corporation

Using Physics of Failure to Predict System Level Reliability for Avionic Electronics

Technical Library | 2013-12-11 23:24:32.0

Today's analyses of electronics reliability at the system level typically use a "black box approach", with relatively poor understanding of the behaviors and performances of such "black boxes" and how they physically and electrically interact (...) The incorporation of more rigorous and more informative approaches and techniques needs to better understand (...) Understanding the Physics of Failure (PoF) is imperative. It is a formalized and structured approach to Failure Analysis/Forensics Engineering that focuses on total learning and not only fixing a particular current problem (...) In this paper we will present an explanation of various physical models that could be deployed through this method, namely, wire bond failures; thermo-mechanical fatigue; and vibration.

DfR Solutions

An Overview of the Intel TFLOPS Supercomputer

Technical Library | 1999-05-07 09:54:35.0

In this paper, we give an overview of the ASCI Option Red Supercomputer. The motivation for building this supercomputer is presented and the hardware and software views of the machine are described in detail. We also briefly discuss what it is like..

Intel Corporation

The Performance of the Intel TFLOPS Supercomputer

Technical Library | 1999-05-07 09:56:38.0

The purpose of building a supercomputer is to provide superior performance on real applications. In this paper, we describe the performance of the Intel TFLOPS Supercomputer starting at the lowest level with a detailed investigation of the Pentium® Pro processor and the supporting memory subsystem.

Intel Corporation

Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for High Performance Flip Chip Package

Technical Library | 2018-01-17 22:47:02.0

Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...) In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published. Originally published in the SMTA International 2016

STATS ChipPAC Inc

Elemental Compositions of Over Two Dozen Cell Phones

Technical Library | 2012-11-08 19:16:39.0

first published in the 2012 IPC APEX EXPO technical conference proceedings. Twenty-nine different cells phones have been disassembled, ground up, dissolved and analyzed for elemental content, mainly for information about the metals present in the phones, but also for some metalloids and non-metals. The paper will discuss the method used and propose possible sources in the telephones for certain elements of interest and the reasons for the interest in some of the elements.

Research In Motion

Reactivity Of No-Clean Flux Residues Trapped Under Bottom Terminated Components

Technical Library | 2017-07-20 15:18:15.0

As electronic devices increase functionality in smaller form factors, there will be limitations, obstacles and challenges to overcome. Advances in component technology can create issues that may have time delayed effects. One such effect is device failure due to soldering residues trapped under bottom terminated components. If the residues trapped under the component termination are active and can be mobilized with moisture, there is the potential for ion mobilization causing current leakage.

Kester

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