Technical Library | 2020-04-14 16:00:20.0
The number of through hole connections on a circuit assembly are decreasing with the drive toward miniaturization. When these assemblies are manufactured in high volumes the most convenient method is selective soldering. Although selective soldering is very well introduced in automotive and industrial applications it can also be a very efficient method to solder high volume consumer products.
Technical Library | 2019-06-03 15:32:40.0
ACI Technologies was pleased to assist a customer by conducting elemental analysis on several assemblies displaying severe corrosion. Several board assemblies had failed in the field and exhibited areas of corrosion in close proximity to onboard components. The most common source of corrosion on electronic assemblies is residual flux. Fluxes are specific chemistries applied during the soldering process which improve the wetting of the solder to both the pad and component when forming the solder joint. They can be highly reactive chemicals that, if left on the assemblies, can lead to corrosion, electrical degradation, and decreased reliability. In the presence of moisture and electrical bias, flux residue can enable dendritic growth as a result of electrochemical migration (ECM).
Technical Library | 2019-05-30 10:59:13.0
In the current economic environment, the ability to reuse ball grid array(BGA) components that have failed due to solder defects may be an efficient way for electronics manufacturers to reduce costs. Cost may not be the only driving factor in the decision to engage in this recycling practice. The increasing demands placed upon the complexity of microprocessors and integrated circuits (ICs) has decreased the availability of some components, and increased their lead time. Because of this, reballing may provide a means to meet schedule, reduce rework turn-around time, and give a manufacturer a decisive advantage over other companies in an ever increasingly competitive market. This article will discuss the process of reballing BGA components (Figure 1), examining preparation (the preform method, the screen method), and cleaning and bake-out.
Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 1999-08-05 10:57:54.0
This study examines ergonomic stressors associated with front-end process tool maintenance, relates them to decreased machine utilization, and proposes solution strategies to reduce their negative impact on productivity.
Technical Library | 2012-03-22 20:40:01.0
Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stacking packages ha
Technical Library | 2015-09-03 18:06:11.0
While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in the interconnections as a means of addressing these issues.
Technical Library | 2015-10-08 17:40:35.0
With the push for ever improving performance on semiconductor component I/O interfaces, semiconductor components are being driven into a realm which makes them more sensitive to electrostatic discharge, potentially increasing in sensitivity by 50% every 3-5 years. Today, the majority of modern day semiconductor components are being designed to meet 250Volts of charge device model sensitivity, and that could decrease to 125Volts in the next 3-5 years, and could again decrease to 50Volts-70Volts in the following 3-5 years. The entire electronics industry must prepare for this challenge.
Technical Library | 2019-02-13 13:45:11.0
Development of information and telecommunications network is outstanding in recent years, and it is required for the related equipment such as communication base stations, servers and routers, to process huge amount of data in no time. As an electrical signal becomes faster and faster, how to prevent signal delay by transmission loss is a big issue for Printed Circuit Boards (PCB) loaded on such equipments. There are two main factors as the cause of transmission loss; dielectric loss and conductor loss. To decrease the dielectric loss, materials having low dielectric constant and low loss tangent have been developed. On the other hand, reducing the surface roughness of the copper foil itself to be used or minimizing the surface roughness by modifying surface treatment process of the conductor patterns before lamination is considered to be effective in order to decrease the conductor loss. However, there is a possibility that reduction in the surface roughness of the conductor patterns will lead to the decrease in adhesion of conductor patterns to dielectric resin and result in the deterioration of reliability of PCB itself. In this paper, we will show the evaluation results of adhesion performance and electrical properties using certain type of dielectric material for high frequency PCB, several types of copper foil and several surface treatment processes of the conductor patterns. Moreover, we will indicate a technique from the aspect of surface treatment process in order to ensure reliability and, at the same time, to prevent signal delay at the signal frequency over 20 GHz.
Technical Library | 2015-05-21 18:46:31.0
In this work the reliability of an embedded planar capacitor laminate under temperature and voltage stress is investigated. The capacitor laminate consisted of an epoxy-BaTiO3 composite sandwiched between two layers of copper. The test vehicle with the embedded capacitors was subjected to a temperature of 125oC and a voltage bias of 200 V for 1000 hours. Capacitance, dissipation factor, and insulation resistance were monitored in-situ. Failed capacitors exhibited a sharp drop in insulation resistance, indicating avalanche breakdown. The decrease in the capacitance after 1000 hours was no more than 8% for any of the devices monitored. The decrease in the capacitance was attributed to delamination in the embedded capacitor laminate and an increase in the spacing between the copper layers.
