Electronics Forum | Wed Aug 21 10:26:08 EDT 2002 | stownsend
We are using OSP coated boards and no-clean solder paste. In a few instances, we are seeing increased distortion in an audio circuit. Has anybody seen or heard of surface insulation resistance (SIR) decreasing after reflow on OSP boards? Is it possib
Electronics Forum | Thu Aug 22 22:07:44 EDT 2002 | davef
Did the techs have a restful night?
Electronics Forum | Wed Aug 21 19:22:44 EDT 2002 | stownsend
Splitting hairs is putting it mildly. I�m just trying to rule out all variables. It doesn�t appear that we have an SIR problem, but since the newest variable is OSP (blame the new guy for all the problems), I have to consider it. I�ve seen this befo
Electronics Forum | Mon Sep 19 09:28:48 EDT 2011 | tech1
And don't break often??? Can you define a time frame for the word "often"
Electronics Forum | Thu Jun 22 17:47:05 EDT 2006 | davef
First, we expect voiding in imm silver to be similar to ENIG. We expect more voiding in OSP than other common solderability protection. Second, choosing a solder paste, which does not contain resins and activators that decompose at higher temperatu
Electronics Forum | Wed Aug 21 17:44:32 EDT 2002 | davef
Splitting hairs, I expect SIR of all solderability protection, including OSP, to decrease after reflow. What�s more, I expect the SIR of all solderability protection to pretty much decrease over time. The �comb pattern� test specimens meet requirem
Electronics Forum | Sat Jun 06 09:53:59 EDT 1998 | Earl Moon
GEOMETRIC DIMENSIONING AND TOLERANCING (GDT) Using and applying GDT to printed circuitry and assemblies is very much like applying it to any other design for manufacturing (DFM) or design for assembly (DFA) requirement using concurrent engineering (C
Electronics Forum | Tue Oct 12 10:24:50 EDT 1999 | Jose RG
Hi, We are in the way to evaluate different solder pastes, improve our solder paste incoming inspection steps, re-define our stencil requirements and the following questions are open. Two questions, 1- Is anybody using/requiring 1000 Kcps or more
Electronics Forum | Tue Dec 13 17:41:04 EST 2011 | davef
A Study Of 0201’s And Tombstoning In Lead-Free Systems, Phase II Comparison Of Final Finishes And Solder Paste Formulations http://sheaengineering.com/Documents/APEX%2008%200201s%20and%20Tombstoning%20phase%202%20paper.pdf CONCLUSION The condition
Electronics Forum | Fri Nov 03 07:28:27 EST 2006 | davef
Via filling methods are: * Tenting * Plugging * Capping * Flooding Tented Via. A via covered with dry film soldermask; the via is not filled. When tenting from both sides there may be issues with trapped air that expands during mass soldering. Plug
