Technical Library: diode and crack (Page 1 of 7)

Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP and Flip Chip Technologies

Technical Library | 2021-01-03 19:24:52.0

Reflow soldering is the primary method for interconnecting surface mount technology (SMT) applications. Successful implementation of this process depends on whether a low defect rate can be achieved. In general, defects often can be attributed to causes rooted in all three aspects, including materials, processes, and designs. Troubleshooting of reflow soldering requires identification and elimination of root causes. Where correcting these causes may be beyond the reach of manufacturers, further optimizing the other relevant factors becomes the next best option in order to minimize the defect rate.

SMTnet

Rework Challenges for Smart Phones and Tablets

Technical Library | 2015-04-23 18:48:18.0

Smart phones are complex, costly devices and therefore need to be reworked correctly the first time. In order to meet the ever-growing demand for performance, the complexity of mobile devices has increased immensely, with more than a 70% greater number of packages now found inside of them than just a few years ago. For instance, 1080P HD camera and video capabilities are now available on most high end smart phones or tablet computers, making their production more elaborate and expensive. The printed circuit boards for these devices are no longer considered disposable goods, and their bill of materials start from $150.00, with higher end smart phones going up to $238.00, and tablets well over $300.00.

Metcal

Flip Chip Attach Techniques

Technical Library | 2019-05-21 17:38:55.0

Last month we presented Flip Chip Rework.As promised, this month we follow up with attachment techniques. Flip chip assembly is a key technology for advanced packaging of microelectronic circuits. It allows attachment of a bare chip to a packaging substrate in a face-down configuration, with electrical connections between the chip and substrate via conducting “bumps.” Flip chip technology was first invented by IBM for mainframe computer application in the early 1960s. Semiconductor devices are mounted face down and electrically and mechanically connected to a substrate (Figure 1). IBM called this manufacturing process a C4 process (controlled collapse chip connection).

ACI Technologies, Inc.

Anisotropic grain growth and crack propagation in eutectic microstructure under cyclic temperature annealing in flip-chip SnPb composite solder joints

Technical Library | 2014-06-19 18:13:23.0

For high-density electronic packaging,the application of flip-chip solder joints has been well received in the microelectronics industry. High-lead(Pb) solders such as Sn5Pb95 are presently granted immunity from the RoHS requirements for their use in high-end flip-chip devices, especially in military applications. In flip-chip technology for consumer electronic products, organic substrates have replaced ceramic substrates due to the demand for less weight and low cost. However, the liquidus temperatures of high-Pb solders are over 300°C which would damage organic substrates during reflow because of the low glass transition temperature. To overcome this difficulty, the composite solder approach was developed...

National Chiao Tung University

PCB Fabrication Processes and Their Effects on Fine Copper Barrel Cracks

Technical Library | 2015-12-23 16:57:27.0

The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.

Raytheon

Best Practices in Selecting Coatings and Pottings for Solar Panel Systems; Junction Boxes and Inverters

Technical Library | 2020-08-13 01:12:57.0

The solar industry has driven solutions that result in electronics systems that are required to perform in outside environments for over 25 years. This industry expectation has resulted in solutions to protect the electronics from failure that can result from interaction with moisture, and various chemicals leading to corrosion and shorting of the systems. Potting and encapsulation compounds can impart the very high level of protection from environmental, thermal, chemical, mechanical, and electrical conditions that the solar applications demand.

DfR Solutions

Reliability and Failure Mechanisms of Laminate Substrates in a Pb-free World

Technical Library | 2009-04-30 18:06:24.0

This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.

i3 Electronics

Defect Features Detected by Acoustic Emission for Flip-Chip CGA/FCBGA/PBGA/FPBGA Packages and Assemblies

Technical Library | 2017-06-22 17:11:53.0

C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination, cracks, voids, and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison, representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques.

Jet Propulsion Laboratory

Laser Solder Reflow: A Process Solution Part I

Technical Library | 2007-09-06 11:03:33.0

EFD Inc. and Leister USA have collaborated to bust the myth that you cannot perform laser reflow with solder paste. Using Leister diode lasers, EFD has formulated solder pastes that survive the rapid reflow cycle typical of laser heating. These solder pastes reflow and wet well, without spatter, even when heating is accomplished in less than half a second. The flux core in wire solders cannot boast such flux spatter resistance in such an aggressive heating environment.

Nordson EFD

Carrier tape introduction and classification

Technical Library | 2019-07-27 07:13:16.0

Carrier Tape refers to a strip product used in the field of electronic packaging, which has a specific thickness, and equidistantly distributes holes (also called pockets) for holding electronic components in the longitudinal direction thereof. Positioning hole for index positioning.

Sewate Technology Co.,Ltd

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