Technical Library | 2019-05-24 09:27:33.0
Decapsulation, or de-cap, is a failure analysis technique which involves the removal of material packaging from an integrated circuit (IC). After de-cap, visual inspection by optical microscopy of the internal circuitry may reveal areas where damage is most likely to have occurred. In addition, scanning electron microscopy (SEM) with energy dispersive x-ray spectroscopy (EDS) can identify the composition of any anomalies present after de-cap under higher magnification. The removal process of package material can be done either mechanically or chemically depending on the design of the integrated circuit. With ceramic packaging, de-cap is usually done mechanically by chiseling off the top with a fine razor and small hammer. For plastic packaging, de-cap requires chemical etching by strong acids. In this Tech Tips article, de-cap by chemical etching will be outlined step by step.
Technical Library | 2019-05-29 10:38:59.0
Decapsulation, or de-cap, is a failure analysis technique which involves the removal of material packaging from an integrated circuit (IC). After de-cap, visual inspection by optical microscopy of the internal circuitry may reveal areas where damage is most likely to have occurred. In addition, scanning electron microscopy (SEM) with energy dispersive x-ray spectroscopy (EDS) can identify the composition of any anomalies present after de-cap under higher magnification. The removal process of package material can be done either mechanically or chemically depending on the design of the integrated circuit. With ceramic packaging, de-cap is usually done mechanically by chiseling off the top with a fine razor and small hammer. For plastic packaging, de-cap requires chemical etching by strong acids. In this Tech Tips article, de-cap by chemical etching will be outlined step by step.
Technical Library | 2019-09-23 09:35:00.0
Failure analysis (FA), by its very nature, is needed only when things goawry. Before any testing is performed on the sample, a decision mustbe made as to whether or not the sample is allowed to be destroyedin the process of testing. Non-destructive testing can allow for re-use of the assembly since the functionality is not altered, but there still remains the possibility that inadvertent damage can occur through the course of the analysis. If non-destructive testing is preferred, then the following types of analysis can be performed. The testing can be divided into four categories: visual, X-ray (X-ray imaging and X-ray fluorescence), cleanliness (resistivity of solvent extract, ion chromatography, and Fourier transform infrared spectroscopy), and mechanical (non-destructive wire bond pull).
Technical Library | 2020-05-08 18:22:31.0
A customer contacted the Helpline to perform analysis on a lead-free assembly which exhibited intermittent functionality. The lead-free assembly exhibiting intermittent functionality when pressure was applied to the ball grid array (BGA) packages. Industrial adaptation of a Restriction of Hazardous Substances (RoHS) compliant solder standard has created a new host of failure modes observed in lead-free assemblies. Pad cratering occurs when fractures propagate along the epoxy resin layer on the underside of the BGA connecting pads. While originating from process, design, and end use conditions, it is the combination of a rigid lead-free solder with inflexible printed circuit board (PCB) laminates that has advanced the prevalence of this condition. Pad cratering is simply the result of mechanical stress exceeding material limitations.
Technical Library | 2010-01-13 12:34:10.0
Micro-sectioning (sometimes referred to as cross-sectioning)is a technique, used to characterize materials or to perform a failure mode analysis, for exposing an internal section of a PCB or package. Destructive in nature, cross-sectioning requires encapsulation of the specimen in order to provide support, stability, and protection. Failures that can be investigated through micro-sectional analysis include component defects, thermo-mechanical failures, processing failures related to solder reflow, opens or shorts, voiding and raw material evaluations.
Technical Library | 2012-12-14 14:28:20.0
This paper examines the potential failure mechanisms that can damage modern lowvoltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms.
Technical Library | 2023-01-23 20:50:05.0
PDC Outline Section 0: Intro Section 1: What is reliability and root cause? Section 2: Overview of failure mechanisms Section 3: Failure analysis techniques – Non-destructive analysis techniques – Destructive analysis – Materials characterization Section 4: Summary and closure
Technical Library | 2009-04-30 18:06:24.0
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.
Technical Library | 2021-07-27 14:49:16.0
Conductive anodic filament (CAF) formation, a failure mode in printed wiring boards (PWBs) that are exposed to high humidity and voltage gradients, has caused catastrophic field failures. CAF is an electrochemical migration failure mechanism in PWBs. In this article, we discuss CAF, the factors that enhance it, and the necessary conditions for its occurrence. Published studies are discussed, and the results of historical mean time to failure models are summarized. Potential reasons for CAF enhancement solutions are discussed, and possible directions in which to develop anti-CAF materials are proposed.
Technical Library | 2020-01-09 00:00:30.0
PCBs have a wide range of applications in electronics where they are used for electric signal transfer. For a multilayer build-up, thin copper foils are alternated with epoxy-based prepregs and laminated to each other. Adhesion between copper and epoxy composites is achieved by technologies based on mechanical interlocking or chemical bonding, however for future development, the understanding of failure mechanisms between these materials is of high importance. In literature, various interfacial failures are reported which lead to adhesion loss between copper and epoxy resins. This review aims to give an overview on common coupling technologies and possible failure mechanisms. The information reviewed can in turn lead to the development of new strategies, enhancing the adhesion strength of copper/epoxy joints and, therefore, establishing a basis for future PCB manufacturing.
