Technical Library: gold plating thickness (Page 1 of 3)

Platings for Interconnections

Technical Library | 2019-06-04 10:19:46.0

Interconnection technology relies very heavily on the ability of the conductors on a printed wiring assembly to maintain reliable signal integrity. Harsh environmental factors can precipitate a loss of conductivity due to oxidation and corrosion. Connections are typically soldered or inserted using pressure fitted connectors to obtain enough surface contact to meet the electrical conductivity requirements. In pressure contacts, surface integrity is especially critical where the abrasive effects of retraction and insertion can wear off the metallic finish from the contact area. This can expose the underlying copper or nickel and lead to increased resistance at the contact points. These types of conductors are frequently found in card edge connectors where the terminations are plated with a layer of nickel and gold (frequently referred to as gold fingers). A hard gold is typically used containing very small amounts of nickel and cobalt to increase the wear resistance.

ACI Technologies, Inc.

Gold Embrittlement In Lead-Free Solder.

Technical Library | 2014-08-07 15:13:44.0

Gold embrittlement in SnPb solder is a well-known failure mechanism in electronic assembly. To avoid this issue, prior studies have indicated a maximum gold content of three weight percent. This study attempts to provide similar guidance for Pb-free (SAC305) solder. Standard surface mount devices were assembled with SnPb and SAC305 solder onto printed boards with various thicknesses of gold plating. The gold plating included electroless nickel immersion gold (ENIG) and electrolytic gold of 15, 25, 35, and 50 microinches over nickel. These gold thicknesses resulted in weight percentages between 0.4 to 7.0 weight percent.

DfR Solutions

Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes

Technical Library | 2014-11-06 16:43:24.0

This paper summarizes the results of recent investigations to examine the effect of electroless nickel process variations with respect to Pb-free (Sn-3.0Ag-0.5Cu) solder connections. These investigations included both ENIG and NiPd as surface finishes intended for second level interconnects in BGA applications. Process variations that are suspected to weaken solder joint reliability, including treatment time and pH, were used to achieve differences in nickel layer composition. Immersion gold deposits were also varied, but were directly dependent upon the plated nickel characteristics. In contrast to gold, different electroless palladium thicknesses were independently achieved by treatment time adjustments.

Atotech

Soldering to Gold Over Nickel Surfaces

Technical Library | 1999-05-07 11:28:39.0

There are many things that can go wrong when soldering to gold plate over nickel surfaces. First of all, we know that gold and solder are not good friends, as any time solder comes into contact with gold, something seems to go wrong. Either the solder bonds to the gold and eventually pulls off as the tin and gold cross-migrate, leaving voids; or the solder completely removes the gold and is expected to bond to the metal which was under the gold.

Kester

Brief description of ENIG for Multilayer PCB

Technical Library | 2013-01-18 02:42:14.0

ENIG (Electroless Nickel/Immersion Gold) is to deposit nickel gold plating which has good solderability, wear resistance , leveling appearance and small electric resistance. It included 4 steps that are pretreatment, immersion nickel, immersion gold and Post treatment...

Everest PCB equipment Co.,Ltd

Factors That Influence Side-Wetting Performance on IC Terminals

Technical Library | 2023-08-04 15:27:30.0

A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.

Texas Instruments

Factors That Influence Side-Wetting Performance on IC Terminals

Technical Library | 2024-04-08 15:46:36.0

A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.

Texas Instruments

Impact of Assembly Cycles on Copper Wrap Plating

Technical Library | 2020-07-22 19:39:05.0

The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures. Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable. The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for a reliable PWB. Minimum copper wrap plating thickness has become an even a bigger concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design. PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching. The companies started a project to study the relationship between Copper wrap plating thickness and via reliability. The project had two phases. This paper will present findings from both Phase 1 and Phase 2.

Firan Technology Group

Challenges on ENEPIG Finished PCBs: Gold Ball Bonding and Pad Metal Lift

Technical Library | 2017-09-07 13:56:11.0

As a surface finish for PCBs, Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized.

Teledyne DALSA

Via Fill and Through Hole Plating Process with Enhanced TH Microdistribution

Technical Library | 2019-07-17 17:56:34.0

The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.

MacDermid Inc.

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