Technical Library: is50 (Page 1 of 1)

A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process

Technical Library | 1999-05-07 10:18:34.0

A novel programmable element has been developed and evaluated for state of the art CMOS processes. This element is based on agglomeration of tVarious aspects of these programmable devices including characterization and optimization of physical and electrical aspects of the element, programming yield, and reliability have been studied. Development ofhe Ti-silicide layer on top of poly fuses.

Intel Corporation

Assessing the Effectiveness of I/O Stencil Aperture Modifications on BTC Void Reduction

Technical Library | 2018-09-26 20:33:26.0

Bottom terminated components, or BTCs, have been rapidly incorporated into PCB designs because of their low cost, small footprint and overall reliability. The combination of leadless terminations with underside ground/thermal pads have presented a multitude of challenges to PCB assemblers, including tilting, poor solder fillet formation, difficult inspection and – most notably – center pad voiding. Voids in large SMT solder joints can be difficult to predict and control due to the variety of input variables that can influence their formation. Solder paste chemistries, PCB final finishes, and reflow profiles and atmospheres have all been scrutinized, and their effects well documented. Additionally, many of the published center pad voiding studies have focused on optimizing center pad footprint and stencil aperture designs. This study focuses on I/O pad stencil modifications rather than center pad modifications. It shows a no-cost, easily implemented I/O design guideline that can be deployed to consistently and repeatedly reduce void formation on BTC-style packages.

AIM Solder