Technical Library: mid chip (Page 1 of 1)

Understanding the Effect of Process Changes and Flux Chemistry on Mid-Chip Solder Balling

Technical Library | 2016-11-30 21:30:50.0

Mid-chip solder balling is a defect typically associated with solder paste exhibiting poor hot slump and/or insufficient wetting during the reflow soldering process, resulting in paste flowing under the component or onto the solder resist. Once molten, this solder is compressed and forced to the side of the component, causing mid-chip solder balling.This paper documents the experimental work performed to further understand the impact on mid-chip solder balling from both the manufacturing process and the flux chemistry.

Henkel Electronic Materials

Gold Stud Bump Flip Chip Bonding on Molded Interconnect Devices

Technical Library | 2015-09-23 22:08:32.0

A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. (...) Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process, thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However, challenges also exist. Few studies have been made on thermocompression bonding on MID substrate, accordingly little information is available on process optimization, material compatibility and bonding reliability. Unlike solder reflow, there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment.

Flex (Flextronics International)

Challenges in Bare Die Mounting

Technical Library | 2014-05-08 16:34:16.0

Bare die mounting on multi-device substrates has been in use in the microelectronics industry since the 1960s. The aerospace industry’s hybrid modules and IBM’s Solid Logic Technology were early implementations that were developed in the 1960’s. The technologies progressed on a steady level until the mid 1990’s when, with the advent of BGA packaging and chip scale packages, the microelectronics industry started a wholesale move to area array packaging. This paper outlines the challenges for both traditional wire-bond die attached to a printed wiring board (pwb), to the more recent applications of bumped die attached to a high performance substrate.

Die Products Consortium

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