Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 1999-08-27 09:29:49.0
Contract packaging houses have to contend with a large mix of die types and products. Flexibility and quick turnaround of package types is a must in this industry. Traditional methods of die encapsulation, (i.e., use of transfer-molding techniques), are only cost effective when producing a large number of components. Liquid encapsulants now provide similar levels of reliability1, and are cost effective...
Technical Library | 2023-09-18 03:53:42.0
好的，以下是根据标题"LED Lens Production Line Solution"写的SEO元描述和标题： SEO Meta Description (300 characters) LED Lens Production Line Solutions: The Complete Package for Efficient and Reliable LED Lens Manufacturing Our LED lens production line solutions are the perfect way to improve your LED lens manufacturing efficiency and reliability. Our solutions include all the equipment and services you need to produce high-quality LED lenses, from lens molding to assembly.
Technical Library | 2023-10-23 18:56:52.0
A thin chip package for off-the-shelf ICs is developed which enables the embedding of these chips into a flexible circuit board. The package consists of a copper fan-out on a polyimide substrate, in which the thinned IC (30um) is embedded. These packages are subsequently integrated in a standard flexible circuit board (FCB). A microcontroller and a proprietary DSP processor are embedded using this technology. The yield of the Ultra-Thin Chip package (UTCP) was measured before embedding in the circuit board, and reaches up to 87% for the packaged microcontrollers (MSP430 family, known-good dies). The yield on the DSP processor was measured to be 62%. After embedding in the FCB, 95% of the functional UTCP-packaged dies are still functional.
Technical Library | 2010-11-18 19:19:50.0
In this article we present both a relatively new and innovative family of packages that is suitable for medium pin count needs and an innovative method for fabricating the substrates for such a package. With respect to lead count, this packaging family is
Technical Library | 2011-10-06 13:59:04.0
The desire to have more functionality into increasingly smaller size end products has been pushing the PCB and IC Packaging industry towards High Density Interconnect (HDI) and 3D Packaging (stacked dies, embedded packaged components). Many companies in the high-end consumer electronics market place have been embedding passive chip components on inner PCB and IC Packages for a few years now. However, embedding packaged components on inner layers has remained elusive for the broader market due to lack of proper design tools and high cost of embedding components on inner layers (...) This paper will highlight several key industrialization aspects addressed in the frame of the European funded FP7 HERMES* project to build a manufacturing environment for products with embedded components. The program entered its third year and is now dealing with the manufacturing of functional demonstrators as an introduction to industrialization.
Technical Library | 2020-09-16 21:24:56.0
Additive manufacturing processes typically used for mechanical parts can be combined with enhanced technologies for electronics production to enable a highly flexible manufacturing of personalized 3D electronic devices. To illustrate different approaches for implementing electrical and electronic functionality, conductive paths and electronic components were embedded in a powder bed printed substrate using an enhanced 3D printer. In addition, a modified Aerosol Jet printing process and assembly technologies adapted from the technology of Molded Interconnect Devices were applied to print circuit patterns and to electrically interconnect components on the surface of the 3D substrates.
Institute for Factory Automation and Production Systems (FAPS)
Technical Library | 2015-01-28 17:39:34.0
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.
Technical Library | 2015-09-03 18:06:11.0
While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in the interconnections as a means of addressing these issues.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
