Technical Library | 2012-02-16 16:53:16.0
Channel simulations are only as accurate as the models used to develop them. While we have seen much effort placed on printed circuit board (PCB) materials (copper finish, dielectric moisture absorption), other elements within the channel have been largel
Technical Library | 2023-11-27 18:29:45.0
This paper examines the modeling of viscoplastic solder behavior in the vicinity of interfacial cracking for flip chip semiconductor packages. Of particular interest is the relationship between viscoplastic deformation in the solder bumps and any possible interface cracking between the epoxy underfill layer and the silicon die. A 3-D finite element code, developed specifically for the study of interfacial fracture problems, was modified to study how viscoplastic solder material properties would affect fracture parameters such as strain energy release rate and phase angle for nearby interfacial cracks. Simplified two-layer periodic symmetry models were developed to investigate these interactions. Comparison of flip chip results using different solder material models showed that viscoplastic models yielded lower stress and fracture parameters than time independent elastic-plastic simulations. It was also found that adding second level attachment greatly increases the magnitude of the solder strain and fracture parameters. As expected, the viscoplastic and temperature dependent elastic-plastic results exhibited greater similarity to each other than results based solely on linear elastic properties. !DOI: 10.1115/1.1649242"
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
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