Technical Library: non and wettign (Page 1 of 10)

Making Sense of Accuracy, Repeatability and Specification for Automated Fluid Dispensing Systems

Technical Library | 2013-11-14 10:43:40.0

Understanding accuracy and repeatability is an important step to analyze fluid dispensing system performance. They can also be prone to misinterpretation when reviewing a product specification. A dispensing motion system can be made to perform better or worse under different operating conditions. This article will explain accuracy and repeatability, and how they can be applied to different specifications. It will also discuss key considerations when interpreting accuracy and repeatability for decision making.

Nordson ASYMTEK

Hand Soldering, Electrical Overstress, and Electrostatic Discharge

Technical Library | 1999-05-09 13:07:16.0

This paper will give the reader a general understanding of EOS and ESD phenomena. It specifically addresses hand soldering's role in EOS and ESD and how to protect against and test for potential problems. It discusses how Metcal Systems address EOS and ESD concerns and how they differ from conventional soldering systems.

Metcal

Combination of Spray and Soak Improves Cleaning under Bottom Terminations

Technical Library | 2014-10-23 18:10:10.0

The functional reliability of electronic circuits determines the overall reliability of the product in which the final products are used. Market forces including more functionality in smaller components, no-clean lead-free solder technologies, competitive forces and automated assembly create process challenges. Cleanliness under the bottom terminations must be maintained in harsh environments. Residues under components can attract moisture and lead to leakage currents and the potential for electrochemical migration (...) The purpose of this research study is to evaluate innovative spray and soak methods for removing low residue flux residues and thoroughly rinsing under Bottom Termination and Leadless Components

KYZEN Corporation

Hand Printing using Nanocoated and other High End Stencil Materials

Technical Library | 2019-05-29 23:10:30.0

There are times when a PCB prototype needs to be built quickly to test out a design. In such cases where it is known early on that there will be multiple iterations or that a "one and done" assembly will be made that there will be some SMT assemblers who choose to hand print solder paste onto the board using a "frameless" stencil. In such cases where hand printing is used, the consistency of the printing technique has typically been in question. Furthermore, the effectiveness of both the nanocoatings as well as the higher end stainless steel materials, which have been heretofore studied in controlled printing environments, will be evaluated for their impact on the hand printing process.The purpose of the study was to determine the effectiveness of select nanocoating materials as well as certain high end stainless steel stencil materials as they relate to the manual SMT printing process. A variety of nanocoatings were applied to SMT metal stencils and solder paste volume measurements were taken to compare the effectiveness.

BEST Inc.

Defect Features Detected by Acoustic Emission for Flip-Chip CGA/FCBGA/PBGA/FPBGA Packages and Assemblies

Technical Library | 2017-06-22 17:11:53.0

C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination, cracks, voids, and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison, representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques.

Jet Propulsion Laboratory

Investigation and Development of Tin-Lead and Lead-Free Solder Pastes to Reduce the Head-In-Pillow Component Soldering Defect.

Technical Library | 2014-03-06 19:04:07.0

Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.

Christopher Associates Inc.

Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP

Technical Library | 2015-12-02 18:32:50.0

(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.

Altera Corporation

Reliability and Failure Mechanisms of Laminate Substrates in a Pb-free World

Technical Library | 2009-04-30 18:06:24.0

This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.

i3 Electronics

When It Comes to Cost Reduction, Variation and Waste are the Enemy

Technical Library | 2009-03-05 15:46:54.0

In a recent survey of 89 organizations conducted by Whataboutquality.com, respondents were asked what few key characteristics defined quality, in the eyes of their customer, the most popular response was: the product or service met my requirements. The next two most popular responses were: it worked like I expected and it was a good value, worth what I paid for it (...) So how do you continue to exceed customer expectations and simultaneously reduce costs? There are two paths to take. You can find and reduce the variation in your process and you can eliminate as much of the non-value-added waste in your operation.

Whataboutquality LLC

Redundancy and High-Volume Manufacturing Methods

Technical Library | 1999-05-07 10:16:31.0

This paper will describe practical aspects of a redundancy implementation on a high-volume cache memory product. Topics covered include various aspects of redundancy from a design and product engineering perspective; and present test development methods for future product implementations.

Intel Corporation

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