Technical Library | 2019-06-04 10:19:46.0
Interconnection technology relies very heavily on the ability of the conductors on a printed wiring assembly to maintain reliable signal integrity. Harsh environmental factors can precipitate a loss of conductivity due to oxidation and corrosion. Connections are typically soldered or inserted using pressure fitted connectors to obtain enough surface contact to meet the electrical conductivity requirements. In pressure contacts, surface integrity is especially critical where the abrasive effects of retraction and insertion can wear off the metallic finish from the contact area. This can expose the underlying copper or nickel and lead to increased resistance at the contact points. These types of conductors are frequently found in card edge connectors where the terminations are plated with a layer of nickel and gold (frequently referred to as gold fingers). A hard gold is typically used containing very small amounts of nickel and cobalt to increase the wear resistance.
Technical Library | 2020-05-08 18:22:31.0
A customer contacted the Helpline to perform analysis on a lead-free assembly which exhibited intermittent functionality. The lead-free assembly exhibiting intermittent functionality when pressure was applied to the ball grid array (BGA) packages. Industrial adaptation of a Restriction of Hazardous Substances (RoHS) compliant solder standard has created a new host of failure modes observed in lead-free assemblies. Pad cratering occurs when fractures propagate along the epoxy resin layer on the underside of the BGA connecting pads. While originating from process, design, and end use conditions, it is the combination of a rigid lead-free solder with inflexible printed circuit board (PCB) laminates that has advanced the prevalence of this condition. Pad cratering is simply the result of mechanical stress exceeding material limitations.
Technical Library | 2022-07-11 09:24:48.0
The change of squeegee pressure has a significant impact on printing. Too small pressure will make the solder paste unable to effectively reach the bottom of the stencil opening and not be well deposited on the pad. Too much pressure will cause tin The paste is printed too thin and can even damage the stencil.
Technical Library | 2023-06-12 18:33:29.0
This paper presents a real-time predictive approach to improve solder paste stencil printing cycle decision making process in surface mount assembly lines. Stencil cleaning is a critical process that influences the quality and efficiency of printing circuit board. Stencil cleaning operation depends on various process variables, such as printing speed, printing pressure, and aperture shape. The objective of this research is to help efficiently decide stencil printing cleaning cycle by applying data-driven predictive methods. To predict the printed circuit board quality level, a recurrent neural network (RNN) is applied to obtain the printing performance for the different cleaning aging. In the prediction model, not only the previous printing performance statuses are included, but also the printing settings are used to enhance the RNN learning. The model is tested using data collected from an actual solder paste stencil printing line. Based on the predicted printing performance level, the model can help automatically identify the possible cleaning cycle in practice. The results indicate that the proposed model architecture can predictively provide accurate solder paste printing process information to decision makers and increase the quality of the stencil printing process.
Technical Library | 2010-04-15 20:42:44.0
The high level of current interest in embedded passives in printed circuit boards is driven by the tremendous pressure to pack more circuitry into smaller spaces. However, adoption has been limited due to design, prototyping and infrastructure issues, as well as the stability and tolerances necessary for widespread replacement of discretes. The focus of this work has been to develop a polymer thick film resistor technology to incorporate reliable organic resistors inside printed wiring boards using standard PWB processing.
Technical Library | 2018-03-07 22:41:05.0
This study investigates the scooping effect during solder paste printing as a function of aperture width, aperture length and squeegee pressure. The percent of the theoretical volume deposited depends on the PWB topography. A typical bimodal percent volume distribution is attributed to poor release apertures and large apertures, where scooping takes place, yielding percent volumes 100%. This printing experiment is done with a concomitant validation of the printing process using standard 3D Solder Paste Inspection (SPI) equipment.
Technical Library | 2012-05-03 20:40:10.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled, un-powered, vec
Technical Library | 2023-05-02 19:06:43.0
As 0402 has become a common package for printed circuit board (PCB) assembly, research and development on mounting 0201 components is emerging as an important topic in the field of surface mount technology for PWB miniaturization. In this study, a test vehicle for 0201 packages was designed to investigate board design and assembly issues. Design of Experiment (DOE) was utilized, using the test vehicle, to explore the influence of key parameters in pad design, printing, pick-andplace, and reflow on the assembly process. These key parameters include printing parameters, mounting height or placement pressure, reflow ramping rate, soak time and peak temperature. The pad designs consist of rectangular pad shape, round pad shape and home-based pad shape. For each pad design, several different aperture openings on the stencil were included. The performance parameters from this experiment include solder paste height, solder paste volume and the number of post-reflow defects. By analyzing the DOE results, optimized pad designs and assembly process parameters were determined.
Technical Library | 2019-05-01 23:18:27.0
Moisture can accelerate various failure mechanisms in printed circuit board assemblies. Moisture can be initially present in the epoxy glass prepreg, absorbed during the wet processes in printed circuit board manufacturing, or diffuse into the printed circuit board during storage. Moisture can reside in the resin, resin/glass interfaces, and micro-cracks or voids due to defects. Higher reflow temperatures associated with lead-free processing increase the vapor pressure, which can lead to higher amounts of moisture uptake compared to eutectic tin-lead reflow processes. In addition to cohesive or adhesive failures within the printed circuit board that lead to cracking and delamination, moisture can also lead to the creation of low impedance paths due to metal migration, interfacial degradation resulting in conductive filament formation, and changes in dimensional stability. Studies have shown that moisture can also reduce the glass-transition temperature and increase the dielectric constant, leading to a reduction in circuit switching speeds and an increase in propagation delay times. This paper provides an overview of printed circuit board fabrication, followed by a brief discussion of moisture diffusion processes, governing models, and dependent variables. We then present guidelines for printed circuit board handling and storage during various stages of production and fabrication so as to mitigate moisture-induced failures.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
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