Technical Library | 1999-08-05 10:34:17.0
This document defines a set of standard test structures with which to benchmark the electrostatic discharge (ESD) robustness of CMOS technologies. The test structures are intended to be used to evaluate the elements of an integrated circuit in the high current and voltage ranges characteristic of ESD events. Test structures are given for resistors, diodes, MOS devices, interconnects, silicon control rectifiers, and parasitic devices. The document explains the implementation strategy and the method of tabulating ESD robustness for various technologies.
Technical Library | 2019-12-30 02:09:39.0
How to choose the material of PCB ? The choice of PCB material must meet the design requirements, the quality of production and cost need to achieve a balance. The design requirements include electrical and institutional parts. This material problem is usually important when designing very high speed PCB boards (frequencies greater than GHz). For example, the commonly used FR-4 material may not be used when dielectric loss at several GHz frequencies, which can have a significant effect on signal attenuation . In the case of electrical, it is important to note whether the dielectric constant and the dielectric loss are combined at the designed frequency
Technical Library | 2010-05-27 22:12:10.0
The quad flat pack no lead or quad flat non-leaded (QFN) is one of the fastest growing package types in the electronics industry today. While the advantages of QFNs are well documented, concerns arise with its reliability and manufacturability. Acceptance of this package, especially in long-life, severe-environment, high-reliability applications, is currently limited. One of the most common drivers for reliability failures is inappropriate adoption of new technologies, such as the case with QFN. In this presentation, we will review and discuss QFN related reliability concerns and challenges, and propose Physics-of-Failure (PoF) based approaches to allow the confident introduction of QFN components into electronics products.
Technical Library | 2009-04-30 19:12:05.0
A brand is the most important strategic asset your business will ever possess. Yet ask even the most experienced marketer and they will struggle to communicate the concept in a single sentence. Furthermore, if you were to approach the majority of today's business-to-business organisations, they would probably tell you that branding finds little application in a market allegedly filled with dispassionate decision makers. However, an increasingly competitive market landscape is eroding this reality - if, indeed, it ever existed. B2B marketing must follow the example of its consumer-focused counterpart and embrace the notion that a strong brand has the power to differentiate, build and protect those it represents in the face of incessant commoditization.
Technical Library | 2011-10-27 18:03:53.0
Leadless, near chip scale packages (LNCSP) like the quad flat pack no lead (QFN) are the fastest growing package types in the electronics industry today. Early LNCSPs were fairly straightforward components with small overall dimensions, a single outer row
Technical Library | 1999-08-05 09:51:47.0
This document summarizes the finding of testing to determine the immunity of semiconductor equipment to voltage sag events. Based in part on the findings, global standards have been adopted to define voltage sag immunity requirements for semiconductor equipment...
Technical Library | 2012-03-15 17:54:47.0
Increases in field-programmable gate array (FPGA) capabilities, combined with growing system complexity, have created many FPGA-based system design challenges. One key challenge is choosing the right FPGA for the design needs, and maximizing the use of FP
Technical Library | 2012-04-19 21:50:46.0
Presented at IPC Apex 2012. Working through the New Product Introduction (NPI) flow between product design and manufacturing is usually a challenging process, with both parties being experts in their own fields and inextricably linked in the flow of g
Technical Library | 1999-05-07 11:35:19.0
Key competitive advantages can be obtained through the minimization of process defects and disruptions. In today's electronic manufacturing processes there are many variables to optimize. By gaining an understanding of what the defects are, and where they come from, is a key step in the process towards defect free/six sigma manufacturing. In the last decade, Surface Mount Technology processes have been slowly converting towards the No-Clean philosophy. This new trend has spawned new processing issues which need to be addressed. This paper will investigate solutions to current problems in the processing of No-Clean SMT processes.
Technical Library | 2007-10-18 13:42:45.0
To successfully achieve lead-free electronics assembly, each participant in the manufacturing process, from purchasing to engineering to maintenance to Quality/Inspection, must have a solid understanding of the changes required of them. This pertains to considerations regarding design, components, PWBs, solder alloys, fluxe s, printing, reflow, wave soldering, rework, cleaning, equipment wear & tear and inspection.