Technical Library: rising (Page 1 of 2)

Vacuum Fluxless Reflow Technology for Fine Pitch First Level Interconnect Bumping Applications

Technical Library | 2023-01-17 17:58:36.0

Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.

Heller Industries Inc.

Augmented-Fin-Air Cooled Heat Sinks

Technical Library | 1999-05-06 10:36:37.0

Augmented-Fin Air-Cooled Heat Sinks Achieve Higher Performance without Significant Rise in Static Pressure Drop.

Aavid Thermalloy, LLC

How To Size Heat Sinks For Semiconductors

Technical Library | 1999-05-06 11:03:39.0

As microprocessor speeds increase, their power needs rise proportionally. This also puts higher demands on the voltage regulator that feeds the processor chip. In spite of the increased power, the regulator chip tends to remain the same size..

Aavid Thermalloy, LLC

Joule Heating Effects on the Current Carrying Capacity of an Organic Substrate for Flip-Chip Applications

Technical Library | 2009-07-22 18:33:41.0

This paper deals with the thermal effects of joule heating in a high interconnect density, thin core, buildup, organic flip chip substrate. The 440 μm thick substrate consists of a 135 μm thick core with via density of about 200 μm. The typical feature sizes in the substrate are 50 micron diameter vias is the core/buildup layers and 12 micron thick metal planes. An experimental test vehicle is powered with current and the temperature rise was measured. A numerical model was used to simulate the temperature rise in the TV.

i3 Electronics

Innovative process for sealing contours protects sensitive components

Technical Library | 2022-09-08 16:40:50.0

Liquid seals in the automotive industry have to meet high functional quality standards and have to be applied in the shortest possible time in view of the high volume of workpieces. This market environment gives rise to innovations that guarantee maximum speed and quality from initial design to final results.

Scheugenpflug Inc.

Phase Convection™: The Lead-Free Solution

Technical Library | 2007-05-30 19:30:22.0

Transition to lead-free is accelerating and when considering constraints related to lead-free and conventional solder pastes, one concern is rising: flexibility. It would be dangerous to commit to lead-free only while the technology is not yet stabilized. Manufacturers need to consider all of the issues related to lead-free and need to find flexible equipment which are able to adapt to both conventional and lead-free constraints.

Vi TECHNOLOGY

Tackling SMT Enemy Number One - Raising The Standard of Solder Paste Application

Technical Library | 2009-05-14 13:57:43.0

Is screen printing technology able to keep pace with rising quality demands and increasingly complex board layouts? Or, is new jet printing technology ready to fill the gap? A comparison study between the two methods reveals some interesting differences. Screen printers offer some possibilities for optimizing solder paste deposits, but optimization is far easier and quicker with the jet printer. At the same time, the ability to print individualized deposits on every single pcb pad may be the ultimate answer to the growing quality challenge.

Mycronic Technologies AB

Today's Vapor Phase Soldering An Optimized Reflow Technology for Lead Free Soldering

Technical Library | 2014-03-20 12:37:39.0

In the beginning of SMT, Vapor Phase Soldering was the preferred reflow soldering technology because of its excellent heat transfer capabilities. There were also some disadvantages like fast temperature rise, nearly no influence on the temperature profiles and high costs. So the use of Vapor Phase Soldering was reduced to special applications with high mass or complex boards in low numbers (e.g. for military or aerospace use).

IBL - Löttechnik GmbH

Characterization, Prevention and Removal of Particulate Matter on Printed Circuit Boards

Technical Library | 2016-12-22 16:44:04.0

Particulate matter contamination is known to become wet and therefore ionically conductive and corrosive if the humidity in the environment rises above the deliquescence relative humidity (DRH) of the particulate matter. In wet condition, particulate matter can electrically bridge closely spaced features on printed circuit boards (PCBs), leading to their electrical failure. (...) The objective of this paper is to develop and describe a practical, routine means of measuring the DRH of minute quantities of particulate matter (1 mg or less) found on PCBs.

IBM Corporation

Defect-Based Test: A Key Enabler for Successful Migration to structural test

Technical Library | 1999-05-06 14:39:20.0

ntelís traditional microprocessor test methodology, based on manually generated functional tests that are applied at speed using functional testers, is facing serious challenges due to the rising cost of manual test generation and the increasing cost of high-speed testers. If current trends continue, the cost of testing a device could exceed the cost of manufacturing it. We therefore need to rely more on automatic test pattern generation (ATPG) and low-cost structural testers.

Intel Corporation

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