Technical Library | 2019-05-21 17:23:47.0
Reflow temperature profiling is the most important aspect of proper control of the solder reflow process. It may appear to some to be a magical art practiced by a select experienced few, who are able to divine the proper settings for a reflow oven by reading graphs as if they were tea leaves. This does not have to be true. This article outlines a systematic method by which engineers and technicians can implement a successful reflow process from scratch.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
Technical Library | 2019-03-25 12:45:56.0
Work instructions are time consuming to generate for engineers, often requiring regeneration from scratch to address very minor changes. They need to be produced in varying levels of detail, with varying guidelines, for multiple stations, operators and lines. Minor component, station or process changes – down to the modification of an individual BOM component – can cause headaches when attempting to maintain consistency across multiple work instructions that are touched by the change.The solution presented here improves efficiency and saves engineering time by making use of a database driven approach. Manufacturing details, component information, process guidelines, annotations, machine-specific data, and more can be stored in one central database. Any information stored in this single repository can then be modified quickly in one location and automatically propagate seamlessly throughout multiple work instructions. These can be instantly printed out or displayed on screens at appropriately affected stations with the simple click of a button, as opposed to regenerating from scratch, or going in and reviewing many documents to find and update with the change.
Technical Library | 2020-08-27 01:15:10.0
Automobile surface defects like scratches or dents occur during the process of manufacturing and cross-border transportation. This will affect consumers' first impression and the service life of the car itself. In most worldwide automobile industries, the inspection process is mainly performed by human vision, which is unstable and insufficient. The combination of artificial intelligence and the automobile industry shows promise nowadays. However, it is a challenge to inspect such defects in a computer system because of imbalanced illumination, specular highlight reflection, various reflection modes and limited defect features. This paper presents the design and implementation of a novel automatic inspection system (AIS) for automobile surface defects which are the located in or close to style lines, edges and handles. The system consists of image acquisition and image processing devices, operating in a closed environment and noncontact way with four LED light sources. Specifically, we use five plane-array Charge Coupled Device (CCD) cameras to collect images of the five sides of the automobile synchronously. Then the AIS extracts candidate defect regions from the vehicle body image by a multi-scale Hessian matrix fusion method. Finally, candidate defect regions are classified into pseudo-defects, dents and scratches by feature extraction (shape, size, statistics and divergence features) and a support vector machine algorithm. Experimental results demonstrate that automatic inspection system can effectively reduce false detection of pseudo-defects produced by image noise and achieve accuracies of 95.6% in dent defects and 97.1% in scratch defects, which is suitable for customs inspection of imported vehicles.
Technical Library | 2015-08-18 14:02:37.0
What is UV Curing? “Ultraviolet (UV) light is an electromagnetic radiation with a wavelength from 400 nm to 100 nm, shorter than that of visible light but longer than X-rays.” (Source: Wikipedia). Ultraviolet or UV curing is used to create a photochemical reaction using high intensity Ultraviolet (UV) energy or “light” to quickly dry inks, adhesives or conformal coatings. Most materials cure with a UV wavelength around 350 ~ 400nm although some materials require UVC energy near 255nm. There are many advantages to using UV curing over other traditional methods of curing. Not only will it increase production speed, it assists in creating a better bond, and improves scratch and solvent resistance. When compared to other methods of curing, UV curing generates a more reliable cured product at a much higher rate of production in a considerably shorter period of time.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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