High Frequency PCB Material: SYTECH Layer Count: 4 layers PCB Thickness: 1.6mm Min. Trace / Space Outer: 0.1mm/0.1mm Min. Drilled Hole: 0.2mm Via Process: Tenting Vias Surface Finish: ENIG+OSP Product Features 1. DK needs to be tiny as well
Thick-Copper PCB Material: Fr-4 Layer Count: 4 layers PCB Thickness: 1.4mm Min. Trace / Space Outer: 0.065mm Min. Drilled Hole: 0.2mm Via Process: Tenting Vias Surface Finish: ENIG Product Features Features: 1) Years of experience in half-
Electronics Forum | Sat Oct 06 08:27:24 EDT 2001 | davef
Yes, some solder masks do not tent well, because the material is too thin. That�s the trade-off. Thin masks: * Conform well to [don't bleed onto] fine pitch features. * Tent vias poorly, requiring an additional "plugging" step. As you imply, if th
Industry News | 2019-11-05 22:07:01.0
Tenting a via refers to covering via with soldermask to enclose or skin over the opening. A via is a hole drilled into the PCB that allows multiple layers on the PCB to be connected to each other. A non tented via is just a via that is not covered with the soldermask layer. Leaving these vias exposed or covered has pros and cons depending on the your design and manufacturing requirements.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
SMTnet Express, June 27, 2019, Subscribers: 32,092, Companies: 10,819, Users: 24,882 Advanced Cu Electroplating Process for Any Layer Via Fill Applications with Thin Surface Copper Credits: MacDermid Inc. Copper-filled micro-vias are a key
Surface Mount Technology Association (SMTA)
subsequent PCB manufacturing process. The through-hole is usually very small, with a diameter of less than 0.35 mm. When the solder resists clogging occurs, there is almost no solder resist oil left in the tent at the opening of the via, and there is a solder resist in the middle of the via or at the bottom of the