Technical Library: underfill and keep and out (Page 1 of 6)

Dam and Fill Encapsulation for Microelectronic Packages

Technical Library | 1999-08-27 09:29:49.0

Contract packaging houses have to contend with a large mix of die types and products. Flexibility and quick turnaround of package types is a must in this industry. Traditional methods of die encapsulation, (i.e., use of transfer-molding techniques), are only cost effective when producing a large number of components. Liquid encapsulants now provide similar levels of reliability1, and are cost effective...


Rework Challenges for Smart Phones and Tablets

Technical Library | 2015-04-23 18:48:18.0

Smart phones are complex, costly devices and therefore need to be reworked correctly the first time. In order to meet the ever-growing demand for performance, the complexity of mobile devices has increased immensely, with more than a 70% greater number of packages now found inside of them than just a few years ago. For instance, 1080P HD camera and video capabilities are now available on most high end smart phones or tablet computers, making their production more elaborate and expensive. The printed circuit boards for these devices are no longer considered disposable goods, and their bill of materials start from $150.00, with higher end smart phones going up to $238.00, and tablets well over $300.00.


Increase Your Process Control and Lower Cost of Ownership

Technical Library | 2012-11-12 14:06:48.0

With consumers constantly looking for lower prices on their technology products and manufacturers trying to squeak out higher margins from their production lines, the need for process control and lower overhead costs have become even more important. One sector that is often overlooked is the hand soldering area of the factory. Many factories have been struggling with antiquated soldering systems for years. In some cases they are trying to make their investment in stations last much longer than they were designed for, or they are falsely trying to recoup their original investment ‐ all at the cost of higher operating expenses or even worse, reduced operator thru‐put.


Combination of Spray and Soak Improves Cleaning under Bottom Terminations

Technical Library | 2014-10-23 18:10:10.0

The functional reliability of electronic circuits determines the overall reliability of the product in which the final products are used. Market forces including more functionality in smaller components, no-clean lead-free solder technologies, competitive forces and automated assembly create process challenges. Cleanliness under the bottom terminations must be maintained in harsh environments. Residues under components can attract moisture and lead to leakage currents and the potential for electrochemical migration (...) The purpose of this research study is to evaluate innovative spray and soak methods for removing low residue flux residues and thoroughly rinsing under Bottom Termination and Leadless Components

KYZEN Corporation

Assembly and Reliability of 1704 I/O FCBGA and FPBGAs

Technical Library | 2013-03-14 17:19:28.0

Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.

Jet Propulsion Laboratory

Status and Outlooks of Flip Chip Technology

Technical Library | 2018-11-14 21:43:14.0

Status of flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill will be reviewed in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. Finally, the competition on flip chip technology will be briefly mentioned.

ASM Pacific Technology

No-Clean Flux Residue and Underfill Compatibility Effects on Electrical Reliability

Technical Library | 2013-04-11 15:43:17.0

With the explosion of growth in handheld electronics devices, manufacturers have been forced to look for ways to reinforce their assemblies against the inevitable bumps and drops that their products experience in the field. One method of reinforcement has been the utilization of underfills to "glue" certain SMDs to the PCB. Bumped SMDs attached to the PCB with a no-clean soldering process offer the unavoidable scenario of the underfill coming in contact with a flux residue. This may or may not create a reliability issue... First published in the 2012 IPC APEX EXPO technical conference proceedings

Indium Corporation

Three-Dimensional MMIC and Its Evolution to WLCSP Technology

Technical Library | 2012-01-19 19:14:49.0

The history of multilayered, three-dimensional monolithic microwave integrated circuit (3-D MMIC) technology is described here. Although significant researches were carried out in the second half of 1990’s, still there were many twists and turns before an

Sumitomo Electric Industries, Ltd.

Evaluation, Selection and Qualification of Replacement Reworkable Underfill Materials

Technical Library | 2019-02-27 15:23:47.0

A study was performed to investigate, evaluate and qualify new reworkable underfill materials to be used primarily with ball grid arrays (BGAs), Leadless SMT devices, QFNs, connectors and passive devices to improve reliability. The supplier of the sole source, currently used underfill, has indicated they may discontinue its manufacture in the near future. The current underfill material is used on numerous circuit card assemblies (CCAs) at several sites and across multiple programs/business areas. In addition, it is used by several of our contract CCA suppliers.The study objectives include evaluation of material properties for down select, dispensability and rework evaluation for further down select, accelerated life testing for final selection and qualification; and process development to implement into production and at our CCA suppliers. The paper will describe the approach used, material property test results and general findings relative to process characteristics and rework ability.

Northrop Grumman Corporation

Temperature Cycling and Fatigue in Electronics

Technical Library | 2020-01-01 17:06:52.0

The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.

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