Thick-Copper PCB Material: Fr-4 Layer Count: 4 layers PCB Thickness: 1.4mm Min. Trace / Space Outer: 0.065mm Min. Drilled Hole: 0.2mm Via Process: Tenting Vias Surface Finish: ENIG Product Features Features: 1) Years of experience in half-
High Frequency PCB Material: SYTECH Layer Count: 4 layers PCB Thickness: 1.6mm Min. Trace / Space Outer: 0.1mm/0.1mm Min. Drilled Hole: 0.2mm Via Process: Tenting Vias Surface Finish: ENIG+OSP Product Features 1. DK needs to be tiny as well
Electronics Forum | Thu Jan 06 08:03:47 EST 2005 | davef
On solder in vias: It looks like the via are not solder masked well and pick-up solder either: * Solder coating ... OR * During leveling It's possible that the design specifies openings in the solder mask for these via. On solder in the unsupporte
Electronics Forum | Mon Jan 11 14:48:44 EST 2010 | davef
SR1000 is commonly used for tenting. Search the fine SMTnet Archives on : tenting Someone gave us this note. We have lost their name. It seems to be good advice. If Liquid Photo Image (LPI) solder mask is required, do not tent via holes. Tenting
Industry News | 2019-11-05 22:07:01.0
Tenting a via refers to covering via with soldermask to enclose or skin over the opening. A via is a hole drilled into the PCB that allows multiple layers on the PCB to be connected to each other. A non tented via is just a via that is not covered with the soldermask layer. Leaving these vias exposed or covered has pros and cons depending on the your design and manufacturing requirements.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."