Technical Library | 2019-05-21 17:38:55.0
Last month we presented Flip Chip Rework.As promised, this month we follow up with attachment techniques. Flip chip assembly is a key technology for advanced packaging of microelectronic circuits. It allows attachment of a bare chip to a packaging substrate in a face-down configuration, with electrical connections between the chip and substrate via conducting “bumps.” Flip chip technology was first invented by IBM for mainframe computer application in the early 1960s. Semiconductor devices are mounted face down and electrically and mechanically connected to a substrate (Figure 1). IBM called this manufacturing process a C4 process (controlled collapse chip connection).
Technical Library | 2020-12-07 15:26:06.0
Temperature cycling testing is a method of accelerated life testing done to PCCs that are exposed to normal operation temperature variations over its lifetime. During the testing, intermittent "open" failures can first occur at the hot and cold extremes of the test, exposing weaknesses in the design and assembly. A poor/weak solder joint fatigues, a via trace or barrel cracks, loose connections or a component fails all causing an intermittent open. When not at extreme temperatures, the PCC assembly relaxes, the "open" closes creating electrical connectivity. If you are monitoring the PCC under test in-situ you will know that an intermittent failure has occurred, and the test could be stopped for inspection. If in-situ monitoring was not implemented, you would not know if there were intermittent failures or not. The PCC gets powered up and works fine at room temperature.
Technical Library | 2019-05-29 01:47:22.0
1.Vias near SMD pads: Solder can flow into the via after melted. As a result cold joint will appear in the end. Check the picture below. 2.Vias on SMD pads: Solder can flow into the via more easier after melted. Check the picture below. 3.Via opening without soldermask covered. When workers solder TH parts by hand, soldering iron can touch vias sometime, then tiny amounts molten solder will stay on vias. This can lead to electrical short easily. We recommend you make all vias tenting (covered by solder mask) if it is possible.
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Technical Library | 2020-07-15 18:49:03.0
Via Filling • Through Hole Vias - IPC-4761 – Plugging – Filling – Filled & Capped • MicroviaFilling and Stacked Vias
Technical Library | 2009-04-30 18:06:24.0
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.
Technical Library | 2001-04-24 10:44:24.0
This paper reviews the possible implementations of the Micro Via Technology within the Mentor Graphic's Board Station environment, specifically within the Librarian, Layout and Fablink applications. In this context, the definition of a Micro Via is constrained to Board Station’s support of such technology and contains only generalized descriptions of the manufacturing processes that require Micro Vias.
Technical Library | 2016-03-03 17:25:26.0
This paper discusses a nano copper based paste for use in via filling. The company manufactures nano copper and disperses the coated nano copper into a paste in combination with micron copper. The resultant paste is injected or fills a via. The via is subsequently sintered by means of photonic sintering, or by heat in a reducing environment. The process will be accomplished in under an hour and results in filled solid copper vias.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
Technical Library | 2013-03-07 18:25:36.0
The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings
