Technical Library: wave and verification (Page 1 of 8)

A Systematic Approach to RoHS Analysis

Technical Library | 2019-07-19 10:21:14.0

One of the most frequently asked questions of ACI Technologies (ACI) is how to qualify and verify that the electronic systems shipped by their respective companies are Restriction of Hazardous Substances (RoHS) compliant. The RoHS directive has been implemented since July of 2006, and the preoccupation with what constitutes a compliant product continues to confuse the electronic industry. ACI receives countless inquiries regarding how to qualify and verify that the electronic systems shipped by the irrespective companies are RoHS compliant. The approach to proving compliancy requires a sequential analytical process that utilizes a decision flow chart.

ACI Technologies, Inc.

Case Study on the Validation of SAC305 and SnCu Based Solders in SMT, Wave and Hand-soldering at the Contract Assembler Level

Technical Library | 2007-11-15 15:54:44.0

At the contractor level once a product is required to be soldered with lead-free solders all the processes must be assessed as to insure the same quality a customer has been accustomed to with a Sn63Pb37 process is achieved. The reflow, wave soldering and hand assembly processes must all be optimized carefully to insure good joint formation as per the appropriate class of electronics with new solder alloys and often new fluxes.

Kester

SnCu Based Alloy Design for Lower Copper Dissolution and Better Process Control

Technical Library | 2009-02-13 12:29:39.0

To meet the market demand for a best-in-class, low-cost leadfree alloy for wave, selective and dip soldering

Kester

Analog FastSPICE Platform Full-Circuit PLL Verification

Technical Library | 2016-06-30 14:00:32.0

When designing PLLs in nanometer CMOS, it is essential to validate the closed-loop PLL performance metrics with nanometer SPICE accuracy before going to silicon. Transistor-level, closed-loop PLL verification has been impractical due to traditional SPICE and RF simulator performance and capacity limitations. By using Analog FastSPICE, designers dont have to trade accuracy for performance. Read this white paper to see how AFS: Delivers closed-loop PLL transistor-level verification Supports direct jitter measurements Produces phase noise results correlating within 1-2dB of silicon

Mentor Graphics

No-Residue Technology Chemistry and Physics

Technical Library | 2004-09-02 11:56:32.0

The main goal of this paper is to highlight the importance of interrelating the physics and the chemistry in wave soldering and soft soldering in general. Often we find the disciplines of chemistry and physics being analyzed distinct and separate. However in the quest for alternative ways for leading edge competitive and especially environmental friendly manufacturing, separating or ignoring this interrelationship is detrimental to the success of No-Residue soldering.

Interflux USA, Inc.

Liquid Tin Corrosion and Lead Free Wave Soldering

Technical Library | 2008-02-12 22:52:41.0

Corrosion of solder pots and solder pot components in wave soldering equipment has been reduced with the introduction of corrosion resistant coatings and improved lead free solder alloys. The latest trends in protecting wave solder machine components from liquid metal corrosion by lead free solder alloys will be presented in order to provide guidelines for evaluating existing equipment as well as for purchasing new systems.

Speedline Technologies, Inc.

The Effect of Coating and Potting on the Reliability of QFN Devices.

Technical Library | 2014-08-28 17:09:23.0

The fastest growing package types in the electronics industry today are Bottom Termination Components (BTCs). While the advantages of BTCs are well documented, they pose significant reliability challenges to users. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies. This is especially true for new component packaging like BTCs. Obtaining relevant information can be difficult since information is often segmented and the focus is on design opportunities not on reliability risks (...)Commonly used conformal coating and potting processes have resulted in shortened fatigue life under thermal cycling conditions. Why do conformal coating and potting reduce fatigue life? This paper details work undertaken to understand the mechanisms underlying this reduction. Verification and determination of mechanical properties of some common materials are performed and highlighted. Recommendations for material selection and housing design are also given.

DfR Solutions

Conformal Surface Plasmons Propagating on Ultrathin and Flexible Films

Technical Library | 2013-09-05 17:44:14.0

Surface plasmon polaritons (SPPs) are localized surface electromagnetic waves that propagate along the interface between a metal and a dielectric. Owing to their inherent subwavelength confinement, SPPs have a strong potential to become building blocks of a type of photonic circuitry built up on 2D metal surfaces; however, SPPs are difficult to control on curved surfaces conformably and flexibly to produce advanced functional devices. Here we propose the concept of conformal surface plasmons (CSPs), surface plasmon waves that can propagate on ultrathin and flexible films to long distances in a wide broadband range from microwave to mid-infrared frequencies.

Southeast University (SEU)

Ready to Start Measuring PCB Warpage during Reflow? Why and How to Use the New IPC-9641 Standard

Technical Library | 2014-08-19 15:39:13.0

Understanding warpage of package attach locations on PCBs under reflow temperature conditions is critical in surface mount technology. A new industry standard, IPC 9641, addresses this topic directly for the first time as an international standard.This paper begins by summarizing the sections of the IPC 9641 standard, including, measurement equipment selection, test setup and methodology, and accuracy verification. The paper goes further to discuss practical implementation of the IPC 9641 standards. Key advantages and disadvantages between available warpage measurement methods are highlighted. Choosing the correct measurement technique depends on requirements for warpage resolution, data density, measurement volume, and data correlation. From industry experience, best practice recommendations are made on warpage management of PCB land areas, covering how to setup, run, analyze, and report on local area PCB warpage.The release of IPC 9641 shows that flatness over temperature of the package land area on the PCB is critical to the SMT industry. Furthermore, compatibility of shapes between attaching surfaces in SMT, like a package and PCB, will be critical to product yield and quality in years to come.

Akrometrix

The Pin-in-Paste (or AART) Process for Odd Form and Through Hole Printed Circuit Boards

Technical Library | 2007-09-27 16:18:15.0

Considerable interest exists in the process known as the pinin- paste, or the Alternative Assembly and Reflow Technology (AART) process. The AART process allows for the simultaneous reflow of both odd-form and through hole devices as well as surface mount components. This process has several advantages over the typical mixed technology process sequence that includes wave soldering and/or hand soldering, often in addition to reflow soldering.

Universal Instruments Corporation

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