Electronics Forum | Mon Oct 25 03:43:26 EDT 1999 | Joe
Hello, Acceptance Quality Levels vary from company to company and product to product. I would like to know what AQL's are being used in the different markets, (military, telecommunucations etc.). What is the standard level used? What
Electronics Forum | Sun May 26 10:21:46 EDT 2002 | V.RAMANAND KINI
We buy PCBs for aluminium wire bonding. Our PCBs have 0.25 mm square pads for bonding and 0.10 or 0.15 mm gap between circuit traces/tracks. We do not have any problem. Our vendor gives 9 microns of Nickel and 0.03 microns of gold.
Electronics Forum | Thu Jun 09 07:02:02 EDT 2005 | ajaydoshi
1. We do have PCB with 0402 component, Micro BGA ( 0.5mm pitch , 0.25 mm pad size ). PCB thickness is 0.8mm. What stencil thickness we should use. PCB size 40 mm X 60 mm 2. We have EKRA E4 , What will be optimum setting for above. Pressure, Scquge s
Electronics Forum | Fri Mar 07 21:02:21 EST 2003 | neil
When printing below .5mm pitch, the recommended stencil thickness is 5Thou, laser cut. Do not use any reduction and ensure wherever possible the pad to space ration is 1:1, the length of the pad is not as important as the gap between adjacent pads. T
Electronics Forum | Mon Mar 19 05:51:24 EDT 2007 | pima
Hello I made some test on different oven and problem still occurs. The only progress is that with diffrent thermoprofil ( Ramp to Spike instead of Ramp- Soak- Spike skewed components appears at 1 % of produced parts). With Ramp - Soak-Spike we have p
Electronics Forum | Wed May 14 21:47:03 EDT 2008 | davef
FAQ from Electronic Imaging Materials site: I am using 0.25-inch high labels in sets of six. How do I print this label configuration using BarTender? In BarTender, first ensure you are using the correct printer driver. Go to File Print and make sur
Electronics Forum | Tue Nov 29 22:32:51 EST 2005 | davef
The dissolution rate of nickel into tin is a lot slower than that of copper [into tin]. This results in a nickel-tin (Ni3Sn4) intermetallic that is only 0.25-0.75�m thin after a normal soldering process. The Ni-Sn intermetallic compound tends to be m
Electronics Forum | Wed Jan 19 22:28:20 EST 2000 | Dave F
Taking things from a slightly different angle: Cost of assembling various packages based on volume: C/R placement: |$0.01 to 0.04 per part SOIC: | $0.03 PLCC based on lead count: | 20-39 $0.16 | 40-59 $0.18 | 60-79 $0.20 | 80-
Electronics Forum | Tue Feb 04 22:28:16 EST 2003 | davef
You could reduce the paste by about 70%. Solder balling and tombstoning will be the issues to fight. The drivers to these don't change with the component size. Use the fine SMTnet Archives for background. Aperture Size and Thickness of Solder Pas
Electronics Forum | Mon Oct 25 16:12:52 EDT 1999 | Joe
Dave: Thanks for the info, I appreciate it. You start off by naming a +/- 2 sigma process, is that equivalant to an AQL of 0.25 ? What is a 6 sigma equivalant to? You mentioned the AQL at incoming inspection, what should that be in relationship to
