Electronics Forum: 1a33 deg c (Page 2 of 44)

Re: seeking low cost fix to tce mismatch

Electronics Forum | Wed Dec 29 15:42:34 EST 1999 | Mike Naddra

Justin, I would be currious as to your customers application, and if the temperature delta and rate are great enough to cause solder joint failures as a function of mismatched Tce then you may want to consider that even if you are able to identify

Board baking after washing machine

Electronics Forum | Thu Nov 01 00:32:14 EST 2001 | ianchan

we bake boards 80~120 deg-C @1hr, after in-line DI wash. oven setting to 90 deg-C, as +/-5 deg-C, tolerance against door open/shut fluctuations = "temperature loss". If anyone has evidenced procedure, that shows no need for baking, pray do share wi

Gold plated PCB's

Electronics Forum | Mon May 06 00:09:00 EDT 2002 | ianchan

as a followup thought, what is your current peak reflow deg-C? and reflow timing (sec)? Au/Ni calls for reflow temperature of 217 deg-C for solder fusion that produces secondary eutectic alloy. there was one time we thought 183 deg-C was the magic

%RH in the Production Hall

Electronics Forum | Mon Jul 17 15:18:31 EDT 2006 | d0min0

Hello there, I'd love to have HR at 50-55%, but also temp at 21-23 deg C, with hot start of summer in Poland, we have on prod.floor close to 30 deg C and 30%HR, it is really difficult to print properly and to get pcb through oven without problems...

CCGA - Stencil design and Reflow Profiling

Electronics Forum | Tue Jul 30 05:26:46 EDT 2019 | ameenullakhan

thanks dave .. I have one more query on the same CCGA. What are the chances of the CCGA lead getting bent or tilt during reflow soldering process. Concern : to achieve the minimum peak temperature of 208 deg C at the connecting leads. On bod

temperature range

Electronics Forum | Mon Nov 20 04:39:19 EST 2000 | SV

Hello, I have to design a PCB for which the customer have the following temperature requirements: -55degC to +85degC operating temp. -61degC to +125degC storage temp. My question is: does the FR4 material meet this conditions? Which are the parame

Re: Poor solder joints on QFP 100's

Electronics Forum | Thu Dec 16 16:46:47 EST 1999 | Mike Naddra

Steve , I use a general set of guidlines when developing reflow profiles: Ramp rate to 140 deg C - 50-60 seconds Time at preheat (140-160 deg C) - 90-120 sec Time above liquidous (183 deg C) - 45-90 sec Time at peak (215-225 deg C) - 9-12 sec peak t

Conversion from SAC305 to SN100C

Electronics Forum | Wed Feb 04 09:44:47 EST 2009 | lococost

It's not a silly arguement. I'm guessing you are talking about wavesoldering? Think about holefill, The reason tin will not fully fill difficult holes is the temperature at the top is too low, it is below the melting point. Increase this melting

vapour phase reflow soldering technology

Electronics Forum | Fri Feb 01 06:15:46 EST 2002 | nifhail

This can be a solution for IC/BGA soldering for lead-free process isn't it ? See, most of the reflow profile set meets solder paste specification but often violating ICs or BGA requirement. Most of the solder paste required temperature of about 205 -

Urethane Coating (1A33)

Electronics Forum | Wed Aug 27 17:12:34 EDT 2008 | mikesewell

Silicone contamination could appear as fisheyes or dark spots under UV light. 1A33 can be heat cured but is a single component oxygen cure coating - it needs a source of oxygen to cure. An unvented oven may slow or limit the cure. Check out the TDS


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