Electronics Forum | Thu Dec 20 19:59:24 EST 2007 | stevek
It's like a QFN with a set of QFP leads around the outside. Looks like a lot of opportunities for problems to me, but folks may have used it, or folks who have totally dialed in QFNs may have ideas.
Electronics Forum | Fri Dec 21 03:21:28 EST 2007 | khushal
Wouldn't it be easier to use a dual row QFN? Have you looked at tsCSP? I think that would be a good options also since it has multiple rows. I am also curious if the tsCSP is just the BCC reborn - any thoughts?
Electronics Forum | Thu Jan 31 20:51:10 EST 2008 | stevek
Wow, they claim 1000 cycles of -65 to 150. I wonder if this was done with the 24mm part. With those tiny joints underneath, they must have exactly matched CTE's with their test boards.
Electronics Forum | Tue May 19 16:30:43 EDT 2009 | base
I've seen a couple of lines of assembleon AX machines in the Micron plant in singapore and at amkor in the philippines. Lines were running smooth and very high yield according to production engineers. Might want to take a look at those machines.
Electronics Forum | Thu Jul 19 21:55:14 EDT 2001 | davef
You're correct, but you need to take it a little bit further. Installed correctly, ExposedPad� TSSOP IC packages significantly increase the thermal efficiency of power constrained standard TSSOP packages. This can increase heat dissipation by as mu
Electronics Forum | Fri Jun 20 18:32:55 EDT 2008 | hegemon
Back when I used to do a lot of these style devices we ran into the same problem you are describing. Use a pattern for the center pad area and keep the total coverage to about 68% of the pad area. Diagonal Stripes, tic tac toe, cloverleaf, dot array
Electronics Forum | Tue May 26 14:39:40 EDT 2009 | boloxis
QFN or MLFs are mainstream now, QFNs already evloved to much more complex versions now like matrix pins, stacked dice and flipchip versions. IPC 610D already includes them, just make sure the pins have solder plating, the PWB pads have soldermask in
Electronics Forum | Fri Jan 03 08:19:24 EST 2003 | emeto
hi, for more info try one of these if you missed some: http://www.amkor.com/ http://ap.pennnet.com/ http://www.asymtek.com http://www.smta.org/ http://www.semiconductor.net/ http://www.smtinfocus.com/ http://www.elis.rug.ac.be/ http://www.kns.com
Electronics Forum | Tue May 26 15:39:16 EDT 2009 | mikesewell
Amkor's MLF guidelines are very similar to Actels. 1 to 1 on the stencil to part pad on the I/O pads, 75% with a grid windowpane, 0.125 mm/5 mil stencil. For example, the Actel area ratio for a 0.3 mm sq. pad and 0.125 mm stencil is 0.6 which seems
Electronics Forum | Fri Apr 12 17:10:41 EDT 2002 | davef
Consider: * Finding JEDEC [ http://www.eia.org/jedec/ ] publication that includes matrix trays is: �JEDEC Publication No.95 Registered and Standard Outlines for Solid State and Related Products�. * Contacting tray manufacturers [ie, Peak, Summit, Nep
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