Electronics Forum | Mon Mar 25 21:50:10 EST 2002 | davef
Some of this was copped from Fred. There are numerous package types that now fall under the rubric of land grid array [LGA]. Land grid devices [ie, Bumped Chip Carrier� [BCC], LGA, Quad Flat-pack No-lead [QFN], MicroLeadFrame�, etc] are essentially
Electronics Forum | Sat Dec 16 10:03:32 EST 2000 | Dave F
Castellation. A recessed metalized feature on the edge of a leadless chip carrier [LCC] that is used to interconnect conducting surface or planes within or on the chip carrier. If you search the fine SMTnet Archives, you find: * A fine thread [cast
Electronics Forum | Thu Jul 30 14:16:32 EDT 1998 | Phil Crane
| WHAT SHOULD THE RATIO BE OF STENCIL APERATURE TO PAD TO GET GOOD QUALITY RESULTS. BY THAT I MEAN, A MINIMM OF SOLDER BALLS, AND LITTLE TO NO BRIDGING, SHORTS, ETC.. | RIGHT NOW WE ARE USING A 1:1 RATIO, BUT ARE INVESTIGATING REDUCING THE APERATU
Electronics Forum | Sun Aug 02 06:54:26 EDT 1998 | Bob Willis
You may liketo contact Chemtech in the UK. http://chemteck.co.uk as they have a new hand book on stencils and a design guide due for release shortly there is also some stencil information as a survey on types and price on my web sites under surveys h
Electronics Forum | Thu Jun 17 21:31:06 EDT 1999 | Dave F
| | Does anyone know where I can find a list of things to do to when troubleshooting issues during the wave solder process? | | | | for example: | | | | Solder Bridge | | 1.verify amount of flux been aplied. | | 2.verify turbulance on your solder w
Electronics Forum | Thu Jun 17 22:10:48 EDT 1999 | Earl Moon
| | | Does anyone know where I can find a list of things to do to when troubleshooting issues during the wave solder process? | | | | | | for example: | | | | | | Solder Bridge | | | 1.verify amount of flux been aplied. | | | 2.verify turbulance on
Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F
=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so
