Electronics Forum: ideally (Page 2 of 48)

BGA Voids

Electronics Forum | Tue Jan 16 13:47:24 EST 2001 | cebukid

10% on various BGA packages. I checked the profile and we are getting "ideal" reflow conditions (~ 60 sec. T.A.L.). Ramp rates, temperature deltas before spike zone, and cooling rates are ideal too. I don't believe it's a profile, print, or paste

Wave Profiling a Ceramic SMT Cap

Electronics Forum | Wed Jan 02 12:32:24 EST 2002 | cebukid

What is the rule-of-thumb on wave profiling Ceramics? I've used 2 methods: 1.) putting the T/C on the lead, and get a pretty good delta (within 50-80 deg. before hitting chip wave), well within manufacturer's spec. 2.) Right on the part body.

Ideal lenght for Selective solder

Electronics Forum | Mon Aug 19 10:25:19 EDT 2013 | jaimebc

Using ERSA Ecoselect. I am curiuos to hear from other selective solder users as to what is the ideal lead lenght for your application on thru hole components. Shorter leads have helped us decrease solder bridges. We find ours to be from .75 mm to 1

Work in Process

Electronics Forum | Thu Feb 24 13:20:40 EST 2000 | Horace Johnson

What software package out there that can manage WIP. We are in the process of consolidating two of our SMT lines into three individual lines for equipment utilization. This will create lots of WIP and need a way to manage it. Any ideals

Work in Process

Electronics Forum | Thu Feb 24 13:20:40 EST 2000 | Horace Johnson

What software package out there that can manage WIP. We are in the process of consolidating two of our SMT lines into three individual lines for equipment utilization. This will create lots of WIP and need a way to manage it. Any ideals

Hover-Davis DDF, what are your opinions?

Electronics Forum | Sat Jan 27 13:44:54 EST 2001 | wbracy

You will find that the DDF feeder was developed around the GSM platform and should be an ideal fit for your application. Email me and I can provide you with contact information and users.

How to calculate ideal WIP at each stations for JIT line

Electronics Forum | Tue Mar 20 05:09:24 EST 2001 | zam_bri

How do we calculate number of board ( WIP ) at every stations for JIT lines. Inputs are welcome.

How to calculate ideal WIP at each stations for JIT line

Electronics Forum | Tue Mar 20 20:07:29 EST 2001 | davef

I can't comment on the firm, but the approach is a good starting point for calculating your Kanbans is with capacity lot sizing http://www.synchronousmanagement.com/cls.html

Adhesive Printing Specification

Electronics Forum | Wed Jul 04 11:07:46 EDT 2001 | a.m.

Hi Mike, What type of component you have the problem? For a quick refernce you have two points for the ideal dot: 1- Dot size = 2/3 of area of glue (pad to pad) 2- Dot height = pad thickness + component stand off

Thermally Conductive Epoxy

Electronics Forum | Wed Aug 01 12:34:12 EDT 2001 | JohnW

The material has to be injected from beneath the component, it's a 240 pin QFP, ideally I wouldn't want the material gong past teh leads as I have to have the option to rework the thing if, perish the thought, it fail's and need's fixed.....


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